Texas Instruments TMS320C67X/C67X+ DSP manual Constraints on Register Reads

Resource Constraints

3.7.6Constraints on Register Reads

More than four reads of the same register cannot occur on the same cycle. Conditional registers are not included in this count.

The following execute packets are invalid:

MPY	.M1	A1, A1, A4 ; five reads of register A1
ADD	.L1	A1, A1, A5
SUB	.D1	A1, A2, A3
MPY	.M1	A1, A1, A4 ; five reads of register A1
ADD	.L1	A1, A1, A5
SUB	.D2x	A1, B2, B3

The following execute packet is valid:

MPY .M1 A1, A1, A4 ; only four reads of A1

[A1] ADD .L1 A0, A1, A5

SUB .D1 A1, A2, A3

3-24 Instruction Set SPRU733