Texas Instruments TMS320C67X/C67X+ DSP manual Stb, Sth, Pipeline Stage Read

STW Store Word to Memory With a 5-Bit Unsigned Constant Offset or Register Offset

Execution

Pipeline

Increments and decrements default to 1 and offsets default to zero when no bracketed register or constant is specified. Stores that do no modification to the baseR can use the syntax *R. Square brackets, [ ], indicate that the ucst5 offset is left-shifted by 2. Parentheses, ( ), can be used to set a nonscaled, constant offset. For example, STW (.unit) src, *+baseR(12) represents an offset of 12 bytes; whereas, STW (.unit) src, *+baseR[12] represents an offset of 12 words, or 48 bytes. You must type either brackets or parentheses around the specified offset, if you use the optional offset parameter.

Word addresses must be aligned on word (two LSBs are 0) boundaries.

if (cond) src → mem else nop

Pipeline	E1
Stage
Read	baseR, offsetR, src
Written	baseR
Unit in use	.D2

Instruction Type	Store
Delay Slots	0
	For more information on delay slots for a store, see Chapter 4.

See Also Example

STB, STH

STW .D1	A1,*++A10[1]
Before	1 cycle after
instruction	instruction

3 cycles after

instruction

A1

A10 mem 100h mem 104h

9A32 7634h

0000 0100h

1111 1134h

0000 1111h

A1

A10 mem 100h mem 104h

9A32 7634h

0000 0104h

1111 1134h

0000 1111h

A1

A10 mem 100h mem 104h

9A32 7634h

0000 0104h

1111 1134h

9A32 7634h

3-246 Instruction Set SPRU733