Texas Instruments TMS320C67X/C67X+ DSP manual Constraints on Floating-Point Instructions, MPYSP2DP

Resource Constraints

3.7.8Constraints on Floating-Point Instructions

If an instruction has a multicycle functional unit latency, it locks the functional unit for the necessary number of cycles. Any new instruction dispatched to that functional unit during this locking period causes undefined results. If an instruction with a multicycle functional unit latency has a condition that is evalu- ated as false during E1, it still locks the functional unit for subsequent cycles.

An instruction of the following types scheduled on cycle i has the following

constraints:
DP compare	No other instruction can use the functional unit on cycles
	i and i + 1.
ADDDP/SUBDP	No other instruction can use the functional unit on cycles
	i and i + 1.
MPYI	No other instruction can use the functional unit on cycles
	i, i + 1, i + 2, and i + 3.
MPYID	No other instruction can use the functional unit on cycles
	i, i + 1, i + 2, and i + 3.
MPYDP	No other instruction can use the functional unit on cycles
	i, i + 1, i + 2, and i + 3.
MPYSPDP	No other instruction can use the functional unit on cycles
	i and i + 1.
MPYSP2DP	No other instruction can use the functional unit on cycles
	i and i + 1.

If a cross path is used to read a source in an instruction with a multicycle func- tional unit latency, you must ensure that no other instructions executing on the same side uses the cross path.

An instruction of the following types scheduled on cycle i using a cross path to read a source, has the following constraints:

DP compare	No other instruction on the same side can used the cross
	path on cycles i and i + 1.
ADDDP/SUBDP	No other instruction on the same side can use the cross
	path on cycles i and i + 1.
MPYI	No other instruction on the same side can use the cross
	path on cycles i, i + 1, i + 2, and i + 3.
MPYID	No other instruction on the same side can use the cross
	path on cycles i, i + 1, i + 2, and i + 3.

3-26 Instruction Set SPRU733