Texas Instruments TMS320C67X/C67X+ DSP manual Tables

Tables

Tables

1−1 Typical Applications for the TMS320 DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32−1 40-Bit/64-Bit Register Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42−2 Functional Units and Operations Performed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52−3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-72−4 Register Addresses for Accessing the Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-82−5 Addressing Mode Register (AMR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-102−6 Block Size Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-122−7 Control Status Register (CSR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-142−8 Interrupt Clear Register (ICR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-162−9 Interrupt Enable Register (IER) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-172−10 Interrupt Flag Register (IFR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-182−11 Interrupt Set Register (ISR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-202−12 Interrupt Service Table Pointer Register (ISTP) Field Descriptions . . . . . . . . . . . . . . . . . . 2-212−13 Control Register File Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-232−14 Floating-Point Adder Configuration Register (FADCR) Field Descriptions . . . . . . . . . . . . 2-242−15 Floating-Point Auxiliary Configuration Register (FAUCR) Field Descriptions . . . . . . . . . . 2-272−16 Floating-Point Multiplier Configuration Register (FMCR) Field Descriptions . . . . . . . . . . 2-313−1 Instruction Operation and Execution Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23−2 Instruction Syntax and Opcode Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73−3 IEEE Floating-Point Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103−4 Special Single-Precision Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-113−5 Hexadecimal and Decimal Representation for Selected Single-Precision Values . . . . . . 3-123−6 Special Double-Precision Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-133−7 Hexadecimal and Decimal Representation for Selected Double-Precision Values . . . . . 3-133−8 Delay Slot and Functional Unit Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-153−9 Registers That Can Be Tested by Conditional Operations . . . . . . . . . . . . . . . . . . . . . . . . . 3-193−10 Indirect Address Generation for Load/Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-333−11 Address Generator Options for Load/Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33

3−12 Relationships Between Operands, Operand Size, Signed/Unsigned,

Functional Units, and Opfields for Example Instruction (ADD) . . . . . . . . . . . . . . . . . . . . . . 3-363−13 Program Counter Values for Example Branch Using a Displacement . . . . . . . . . . . . . . . . 3-703−14 Program Counter Values for Example Branch Using a Register . . . . . . . . . . . . . . . . . . . . 3-723−15 Program Counter Values for B IRP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-743−16 Program Counter Values for B NRP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-763−17 Data Types Supported by LDB(U) Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1233−18 Data Types Supported by LDB(U) Instruction (15-Bit Offset) . . . . . . . . . . . . . . . . . . . . . . 3-126

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