Texas Instruments TMS320C67X/C67X+ DSP Table 441. Loads in Pipeline from Example 42, Figure 434. 8-Bank Interleaved Memory With Two Memory Spaces

Performance Considerations
4-63PipelineSPRU733
Table 4−41. Loads in Pipeline from Example 4−2
ii + 1 i + 2 i + 3 i + 4 i + 5
LDW .D1
Bank 0
E1 E2 E3 −E4 E5
LDW .D2
Bank 0
E1 E2 −E3 E4 E5
For devices that have more than one memory space (see Figure 4−34), an
access to bank 0 in one space does not interfere with an access to bank 0 in
another memory space, and no pipeline stall occurs.
The internal memory of the C67x DSP family varies from device to device. See
the device-specific data manual to determine the memory spaces in your device.
Figure 4−34. 8-Bank Interleaved Memory With Two Memory Spaces
Bank 7Bank 6Bank 5Bank 4Bank 3Bank 2Bank 1
+1M
Bank 0
16N 16N 16N 16N 16N 16N 16N 16N 16N 16N 16N 16 N 16N 16N 16N16N
01
16 17
Bank 0
23
18 19
Bank 1
45
20 21
Bank 2
67
22 23
Bank 3
89
24 25
Bank 4
10 11
26 27
Bank 5
12 13
28 29
Bank 6
14 15
30 31
Bank 7
+++++++++++++++123456789 011112131415
16 16M 16M 16 M 16M 16M 16M 16M 16M 16M 16M 16M 16M 16M 16M16M ++ ++ ++ ++ + + ++ ++23 45 67 89 011112131415
Memory space 1
Memory space 0