Texas Instruments TMS320C67X/C67X+ DSP manual 1. Operations Occurring During Pipeline Phases

			Pipeline Operation Overview
Table 4−1. Operations Occurring During Pipeline Phases
				Instruction
				Type
Stage	Phase	Symbol	During This Phase	Completed
Program	Program address	PG	The address of the fetch packet is determined.
fetch	generation
	Program address	PS	The address of the fetch packet is sent to the memory.
	sent
	Program wait	PW	A program memory access is performed.
	Program data	PR	The fetch packet is at the CPU boundary.
	receive
Program	Dispatch	DP	The next execute packet of the fetch packet is deter-
decode			mined and sent to the appropriate functional unit to be
			decoded.
	Decode	DC	Instructions are decoded in functional units.
Execute	Execute 1	E1	For all instruction types, the conditions for the	Single-cycle
			instructions are evaluated and operands are read.

For load and store instructions, address generation is performed and address modifications are written to the register file.†

For branch instructions, branch fetch packet in PG phase is affected.†

For single-cycle instructions, results are written to a register file.†

For DP compare, ADDDP/SUBDP, and MPYDP instructions, the lower 32-bits of the sources are read. For all other instructions, the sources are read.†

For MPYSPDP instruction, the src1 and the lower 32 bits of src2 are read.†

For 2-cycle DP instructions, the lower 32 bits of the result are written to a register file.†

†This assumes that the conditions for the instructions are evaluated as true. If the condition is evaluated as false, the instruction does not write an y results or have any pipeline operation after E1.

SPRU733 Pipeline 4-7