Texas Instruments TMS320C67X/C67X+ DSP manual Traps, Example 5−15. Code Sequence to Invoke a Trap

Programming Considerations

5.6.4Traps

A trap behaves like an interrupt, but is created and controlled with software. The trap condition can be stored in any one of the conditional registers: A1, A2, B0, B1, or B2. If the trap condition is valid, a branch to the trap handler routine processes the trap and the return.

Example 5−15 and Example 5−16 show a trap call and the return code sequence, respectively. In the first code sequence, the address of the trap handler code is loaded into register B0 and the branch is called. In the delay slots of the branch, the context is saved in the B0 register, the GIE bit is cleared to disable maskable interrupts, and the return pointer is stored in the B1 register. If the trap handler were within the 21-bit offset for a branch using a displacement, the MVKH instructions could be eliminated, thus shortening the code sequence.

The trap is processed with the code located at the address pointed to by the label TRAP_HANDLER. If the B0 or B1 registers are needed in the trap handler, their contents must be stored to memory and restored before return- ing. The code shown in Example 5−16 should be included at the end of the trap handler code to restore the context prior to the trap and return to the TRAP_RETURN address.

Example 5−15. Code Sequence to Invoke a Trap

[A1]	MVK	TRAP_HANDLER,B0	; load 32-bit trap address
[A1]	MVKH	TRAP_HANDLER,B0
[A1]	B	B0	; branch to trap handler
[A1]	MVC	CSR,B0	; read CSR
[A1]	AND	-2,B0,B1	; disable interrupts: GIE = 0
[A1]	MVC	B1,CSR	; write to CSR
[A1]	MVK	TRAP_RETURN,B1	; load 32-bit return address
[A1]	MVKH	TRAP_RETURN,B1
TRAP_RETURN:		(post-trap code)

Note: A1 contains the trap condition.

Example 5−16. Code Sequence for Trap Return

B	B1	; return
MVC	B0,CSR	; restore CSR
NOP	4	; delay slots

5-26 Interrupts SPRU733