Texas Instruments TMS320C67X/C67X+ DSP manual 131

		Tables
3−19	Data Types Supported by LDH(U) Instruction	3-131
3−20	Data Types Supported by LDH(U) Instruction (15-Bit Offset)	3-135
3−21	Register Addresses for Accessing the Control Registers	3-182
4−1	Operations Occurring During Pipeline Phases	. . 4-7
4−2	Execution Stage Length Description for Each Instruction Type	. 4-12
4−3	Single-Cycle Instruction Execution	. 4-16
4−4	16 ⋅ 16-Bit Multiply Instruction Execution	. 4-17
4−5	Store Instruction Execution	. 4-18
4−6	Load Instruction Execution	. 4-20
4−7	Branch Instruction Execution	. 4-22
4−8	Two-Cycle DP Instruction Execution	. 4-24
4−9	Four-Cycle Instruction Execution	. 4-25
4−10	INTDP Instruction Execution	. 4-26
4−11	DP Compare Instruction Execution	. 4-27
4−12	ADDDP/SUBDP Instruction Execution	. 4-28
4−13	MPYI Instruction Execution	. 4-29
4−14	MPYID Instruction Execution	. 4-30
4−15	MPYDP Instruction Execution	. 4-31
4−16	MPYSPDP Instruction Execution	. 4-32
4−17	MPYSP2DP Instruction Execution	. 4-33
4−18	Single-Cycle .S-Unit Instruction Constraints	. 4-34
4−19	DP Compare .S-Unit Instruction Constraints	. 4-35
4−20	2-Cycle DP .S-Unit Instruction Constraints	. 4-36
4−21	ADDSP/SUBSP .S-Unit Instruction Constraints	. 4-37
4−22	ADDDP/SUBDP .S-Unit Instruction Constraints	. 4-38
4−23	Branch .S-Unit Instruction Constraints	. 4-39
4−24	16 ⋅ 16 Multiply .M-Unit Instruction Constraints	. 4-40
4−25	4-Cycle .M-Unit Instruction Constraints	. 4-41
4−26	MPYI .M-Unit Instruction Constraints	. 4-42
4−27	MPYID .M-Unit Instruction Constraints	. 4-43
4−28	MPYDP .M-Unit Instruction Constraints	. 4-44
4−29	MPYSP .M-Unit Instruction Constraints	. 4-45
4−30	MPYSPDP .M-Unit Instruction Constraints	. 4-46
4−31	MPYSP2DP .M-Unit Instruction Constraints	. 4-47
4−32	Single-Cycle .L-Unit Instruction Constraints	. 4-48
4−33	4-Cycle .L-Unit Instruction Constraints	. 4-49
4−34	INTDP .L-Unit Instruction Constraints	. 4-50
4−35	ADDDP/SUBDP .L-Unit Instruction Constraints	. 4-51
4−36	Load .D-Unit Instruction Constraints	. 4-52
4−37	Store .D-Unit Instruction Constraints	. 4-53
4−38	Single-Cycle .D-Unit Instruction Constraints	. 4-54
4−39	LDDW Instruction With Long Write Instruction Constraints	. 4-55
4−40	Program Memory Accesses Versus Data Load Accesses	. 4-60
4−41	Loads in Pipeline from Example 4−2	. 4-63

SPRU733 Tables xv