Parallel Operations

Example 3−1. Fully Serial p-Bit Pattern in a Fetch Packet

This p-bit pattern:

31

0

31

0

31

0

31

0

31

0

31

0

31

0

31

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction

 

Instruction

 

Instruction

 

Instruction

 

Instruction

 

Instruction

 

Instruction

 

Instruction

 

A

 

B

 

C

 

D

 

E

 

F

 

G

 

H

 

results in this execution sequence:

Cycle/Execute

 

Packet

Instructions

1A

2B

3C

4D

5E

6

F

7G

8H

The eight instructions are executed sequentially.

Example 3−2. Fully Parallel p-Bit Pattern in a Fetch Packet

This p-bit pattern:

31

0

31

0

31

0

31

0

31

0

31

0

31

0

31

0

 

1

 

1

 

1

 

1

 

1

 

1

 

1

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction

 

Instruction

 

Instruction

 

Instruction

 

Instruction

 

Instruction

 

Instruction

 

Instruction

 

A

 

B

 

C

 

D

 

E

 

F

 

G

 

H

 

results in this execution sequence:

Cycle/Execute

 

 

 

 

 

 

 

 

Packet

 

 

 

 

Instructions

 

 

 

 

 

 

 

 

 

 

 

 

1

A

B

C

D

E

F

G

H

 

 

 

 

 

 

 

 

 

All eight instructions are executed in parallel.

SPRU733

Instruction Set

3-17

Page 77
Image 77
Texas Instruments TMS320C67X/C67X+ DSP manual Example 3−1. Fully Serial p-Bit Pattern in a Fetch Packet, Cycle/Execute