Texas Instruments TMS320C67X/C67X+ DSP manual Ldbu, Register Offset, Left Shift

			Load Byte From Memory With a 5-Bit Unsigned Constant Offset or Register Offset														LDB(U)
				Load Byte From Memory With a 5-Bit Unsigned Constant Offset or
LDB(U)
				Register Offset
Syntax					Register Offset					Unsigned Constant Offset
					LDB (.unit) *+baseR[offsetR], dst					LDB (.unit) *+baseR[ucst5], dst
					or					or
					LDBU (.unit) *+baseR[offsetR], dst					LDBU (.unit) *+baseR[ucst5], dst
					.unit = .D1 or .D2
Compatibility					C62x, C64x, C67x, and C67x+ CPU
Opcode
31	29	28	27	23		22	18	17	13	12	9	8	7	6	4	3	2	1	0

creg

z

dst

baseR

offsetR/ucst5

mode

0y

op

0 1 s

p

3	1	5	5	5	4	1	3	1	1
Description			Loads a byte from memory to a general-purpose register (dst). Table 3−17
			summarizes the data types supported by loads. Table 3−11 (page 3-33)
			describes the addressing generator options. The memory address is formed

from a base address register (baseR) and an optional offset that is either a register (offsetR) or a 5-bit unsigned constant (ucst5). If an offset is not given, the assembler assigns an offset of zero.

offsetR and baseR must be in the same register file and on the same side as the .D unit used. The y bit in the opcode determines the .D unit and register file used: y = 0 selects the .D1 unit and baseR and offsetR from the A register file, and y = 1 selects the .D2 unit and baseR and offsetR from the B register file.

offsetR/ucst5 is scaled by a left-shift of 0 bits. After scaling, offsetR/ucst5 is added to or subtracted from baseR. For the preincrement, predecrement, pos- itive offset, and negative offset address generator options, the result of the calculation is the address to be accessed in memory. For postincrement or postdecrement addressing, the value of baseR before the addition or subtrac- tion is the address to be accessed in memory.

Table 3−17. Data Types Supported by LDB(U) Instruction

		op				Left Shift of
Mnemonic	Field			Load Data Type	SIze	Offset
LDB	0	1	0	Load byte	8	0 bits
LDBU	0	0	1	Load byte unsigned	8	0 bits

SPRU733 Instruction Set 3-123