Texas Instruments TMS320C67X/C67X+ DSP manual Unit No unit instructions

Index

multiply (continued) unsigned by unsigned

unsigned 16 LSB by unsigned 16 LSB (MPYU) 3-174

unsigned 16 LSB by unsigned 16 MSB (MPYLHU) 3-163

unsigned 16 MSB by unsigned 16 LSB (MPYHLU) 3-151

unsigned 16 MSB by unsigned 16 MSB (MPYHU) 3-154

multiply instructions

.M-unit instruction constraints 4-40block diagram 4-17

pipeline operation 4-17MV instruction 3-178MVC instruction 3-180MVK instruction 3-183MVKH instruction 3-185MVKL instruction 3-187MVKLH instruction 3-185

N

NAN1 bit

in FADCR 2-24

in FAUCR 2-27

in FMCR 2-31

NAN2 bit

in FADCR 2-24

in FAUCR 2-27

in FMCR 2-31NEG instruction 3-189negate (NEG) 3-189nested interrupts 5-23

NMI return pointer register (NRP) 2-22

NMIE bit	2-17
NMIF bit	2-18
no operation (NOP)		3-190
NOP instruction 3-190
NORM instruction		3-192

normalize integer (NORM) 3-192NOT instruction 3-194notational conventions iii

NRP 2-22

O

opcode, fields and meanings 3-7

opcode map
.D unit	C-3
.L unit	D-3
.M unit	E-3
.S unit	F-3
32-bit
.D unit		C-5
.L unit		D-4
.M unit		E-4
.S unit		F-4
no unit instructions			G-3
no unit instructions G-2
symbols and meanings
.D unit		C-3
.L unit		D-3
.M unit		E-3
.S unit		F-3
no unit instructions			G-2

operands, examples 3-35options 1-4

OR instruction 3-195

OVER bit

in FADCR 2-24

in FAUCR 2-27

in FMCR 2-31

overview interrupts 5-2

TMS320 DSP family 1-2TMS320C6000 DSP family 1-2

P

parallel code 3-18parallel fetch packets 3-17

parallel operations 3-16

branch into the middle of an execute packet 3-18

parallel code 3-18

partially serial fetch packets 3-18PCC bits 2-13

PCE1 2-22

performance considerations interrupts 5-21pipeline 4-56

PG pipeline phase 4-2

Index-8 SPRU733