Texas Instruments TMS320C67X/C67X+ DSP manual Reset

Index

IEn bit 2-17
IER 2-17
IFn bit 2-18
IFR 2-18
INEX bit
in FADCR		2-24
in FAUCR		2-27
in FMCR		2-31
INFO bit
in FADCR		2-24
in FAUCR		2-27
in FMCR		2-31
instruction compatibility			3-34,A-1
instruction descriptions			3-34
instruction execution
.D unit	C-2
.L unit	D-2
.M unit	E-2
.S unit	F-2
no unit instructions			G-2

instruction operation, notations 3-2instruction to functional unit mapping B-1

instruction types
ADDDP instruction			4-28
branch instructions			4-22
DP compare	4-27
four-cycle 4-25
INTDP instruction			4-26
load instructions		4-20
MPYDP instruction			4-31
MPYI instruction		4-29
MPYID instruction			4-30
MPYSPDP instruction 4-32
MPYSP2DP instruction				4-33
multiply instructions			4-17
single-cycle 4-16
store instructions		4-18
SUBDP instruction			4-28
two-cycle DP	4-24
INTDP instruction	3-117
.L-unit instruction constraints					4-50
pipeline operation			4-26
INTDPU instruction		3-119
interleaved memory bank scheme					4-62
8-bank memory
single memory space				4-62
with two memory spaces 4-63
interrupt clear register (ICR)				2-16

interrupt enable register (IER)									2-17
interrupt flag register (IFR)								2-18
interrupt return pointer register (IRP)											2-19
interrupt service fetch packet (ISFP)											5-7
interrupt service table (IST)								5-6
interrupt service table pointer (ISTP), overview												5-9
interrupt service table pointer register (ISTP)												2-21
interrupt set register (ISR)								2-20
interrupts
clearing	5-14
control	5-13
control registers				5-10
detection and processing								5-16
actions taken during nonreset interrupt
processing				5-18
actions taken during										interrupt
							RESET
processing				5-20
conditions for processing a nonreset
interrupt			5-16
setting the nonreset interrupt flag 5-16
setting the						interrupt flag					5-19
		RESET
disabling	5-13
enabling	5-13
global control			5-11
globally disabling				5-11
globally enabling				5-11
overview	5-2
performance considerations									5-21
frequency			5-21
latency 5-21
overhead			5-21
pipeline interaction 5-21
pipeline interaction
branches			5-21
code parallelism					5-21
memory stalls				5-21
multicycle NOPs					5-21
priorities	5-3
programming considerations									5-22
manual interrupt processing 5-25
nested interrupts					5-23
single assignment					5-22
traps	5-26
returning from interrupt servicing											5-15
setting	5-14
signals used			5-2
status 5-14
types of	5-2
INTSP instruction			3-121

SPRU733 Index-5