Texas Instruments TMS320C67X/C67X+ DSP manual Ldb, Ldw, Pipeline Stage Read

LDH(U) Load Halfword From Memory With a 5-Bit Unsigned Constant Offset or Register Offset

Execution

Pipeline

The addressing arithmetic that performs the additions and subtractions defaults to linear mode. However, for A4−A7 and for B4−B7, the mode can be changed to circular mode by writing the appropriate value to the AMR (see section 2.7.3, page 2-10).

For LDH(U), the values are loaded into the 16 LSBs of dst. For LDH, the upper 16 bits of dst are sign-extended; for LDHU, the upper 16 bits of dst are zero- filled. The s bit determines which file dst will be loaded into: s = 0 indicates dst will be loaded in the A register file and s = 1 indicates dst will be loaded in the B register file. The r bit should be cleared to 0.

Increments and decrements default to 1 and offsets default to 0 when no bracketed register or constant is specified. Loads that do no modification to the baseR can use the syntax *R. Square brackets, [ ], indicate that the ucst5 offset is left-shifted by 1. Parentheses, ( ), can be used to set a nonscaled, constant offset. You must type either brackets or parentheses around the specified offset, if you use the optional offset parameter.

Halfword addresses must be aligned on halfword (LSB is 0) boundaries.

if (cond) mem → dst else nop

Pipeline	E1	E2	E3	E4	E5
Stage
Read	baseR
	offsetR
Written	baseR				dst
Unit in use	.D

Instruction Type	Load
Delay Slots	4 for loaded value
	0 for address modification from pre/post increment/decrement
	For more information on delay slots for a load, see Chapter 4.
See Also	LDB, LDW

3-132 Instruction Set SPRU733