Texas Instruments TMS320C67X/C67X+ DSP manual Setting the Reset Interrupt Flag, Ps Pw Pr Dp Dc

Interrupt Detection and Processing

5.4.4Setting the RESET Interrupt Flag

RESET must be held low for a minimum of 10 clock cycles. Four clock cycles after RESET goes high, processing of the reset vector begins. The flag for RESET (IF0) in the IFR is set by the low-to-high transition of the RESET signal on the CPU boundary. In Figure 5−5, IF0 is set during CPU cycle 15. This tran- sition is detected on a clock-cycle by clock-cycle basis and is not affected by memory stalls that might extend a CPU cycle.

Figure 5−5. RESET Interrupt Detection and Processing: Pipeline Operation

Clock cycle 0			1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22
	RESET
	at pin																{
	IF0
	IACK
	INUM	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Execute

packet

nE1 E2

n+1 DC E1

n+2 DP DC

	n+3	PR	DP		Pipeline flush
	n+4	PW PR
	n+5	PS	PW
								Cycles 15 −21:		}
	n+6	PG	PS
							Nonreset interrupt
	n+7		PG			processing is disabled
	Reset ISFP					PG		PS PW PR	DP DC	E1
CPU cycle		0	1 2	3 4 5 6 7 8 9 10 11 12 13 14 15 16				17 18 19	20 21	22

†IF0 is set on the next CPU cycle boundary after a 4-clock cycle delay after the rising edge of RESET.

‡After this point, interrupts are still disabled. All nonreset interrupts are disabled when NMIE = 0. All maskable interrupts are disabled when GIE = 0.

SPRU733 Interrupts 5-19