Figures

 

 

 

4−18

Two-Cycle DP Instruction Phases

. . 4-24

4−19

Four-Cycle Instruction Phases

. . 4-25

4−20

INTDP Instruction Phases

. . 4-26

4−21

DP Compare Instruction Phases

. . 4-27

4−22

ADDDP/SUBDP Instruction Phases

. . 4-28

4−23

MPYI Instruction Phases

. . 4-29

4−24

MPYID Instruction Phases

. . 4-30

4−25

MPYDP Instruction Phases

. . 4-31

4−26

MPYSPDP Instruction Phases

. . 4-32

4−27

MPYSP2DP Instruction Phases

. . 4-33

4−28

Pipeline Operation: Fetch Packets With Different Numbers of Execute Packets

. . 4-57

4−29

Multicycle NOP in an Execute Packet

. . 4-58

4−30

Branching and Multicycle NOPs

. . 4-59

4−31

Pipeline Phases Used During Memory Accesses

. . 4-60

4−32

Program and Data Memory Stalls

. . 4-61

4−33

8-Bank Interleaved Memory

. . 4-62

4−34

8-Bank Interleaved Memory With Two Memory Spaces

. . 4-63

5−1

Interrupt Service Table

. . . 5-6

5−2

Interrupt Service Fetch Packet

. . . 5-7

5−3

Interrupt Service Table With Branch to Additional Interrupt Service Code

 

 

Located Outside the IST

. . . 5-8

5−4

Nonreset Interrupt Detection and Processing: Pipeline Operation

. . 5-17

5−5

RESET Interrupt Detection and Processing: Pipeline Operation

. . 5-19

C−1

1 or 2 Sources Instruction Format

. . . C-5

C−2

Extended .D Unit 1 or 2 Sources Instruction Format

. . . C-5

C−3

Load/Store Basic Operations

. . . C-5

C−4

Load/Store Long-Immediate Operations

. . . C-5

D−1

1 or 2 Sources Instruction Format

. . . D-4

D−2

1 or 2 Sources, Nonconditional Instruction Format

. . . D-4

D−3

Unary Instruction Format

. . . D-4

E−1

Extended M-Unit with Compound Operations

. . . E-4

E−2

Extended .M Unit 1 or 2 Sources, Nonconditional Instruction Format

. . . E-4

E−3

Extended .M-Unit Unary Instruction Format

. . . E-4

F−1

1 or 2 Sources Instruction Format

. . . F-4

F−2

Extended .S Unit 1 or 2 Sources Instruction Format

. . . F-4

F−3

Extended .S Unit 1 or 2 Sources, Nonconditional Instruction Format

. . . F-4

F−4

Unary Instruction Format

. . . F-4

F−5

Extended .S Unit Branch Conditional, Immediate Instruction Format

. . . F-4

F−6

Call Unconditional, Immediate with Implied NOP 5 Instruction Format

. . . F-5

F−7

Branch with NOP Constant Instruction Format

. . . F-5

F−8

Branch with NOP Register Instruction Format

. . . F-5

F−9

Branch Instruction Format

. . . F-5

F−10

MVK Instruction Format

. . . F-5

F−11

Field Operations

. . . F-5

G−1

Loop Buffer Instruction Format

. . . G-3

G−2

NOP and IDLE Instruction Format

. . . G-3

G−3

Emulation/Control Instruction Format

. . . G-3

SPRU733

Figures

xiii

Page 13
Image 13
Texas Instruments TMS320C67X/C67X+ DSP manual 18