Texas Instruments TMS320C67X/C67X+ DSP manual Two-Cycle DP Instructions

Pipeline Execution of Instruction Types

4.2.6Two-Cycle DP Instructions

Two-cycle DP instructions use both the E1 and E2 phases of the pipeline to complete their operations (see Table 4−8). The following instructions are two-cycle DP instructions:

-ABSDP

-RCPDP

-RSQDP

-SPDP

The lower and upper 32 bits of the DP source are read on E1 using the src1 and src2 ports, respectively. The lower 32 bits of the DP source are written on E1 and the upper 32 bits of the DP source are written on E2. The two-cycle DP instructions are executed on the .S units. The status is written to the FAUCR on E1. Figure 4−18 shows the fetch, decode, and execute phases of the pipe- line that the two-cycle DP instructions use.

Table 4−8. Two-Cycle DP Instruction Execution

Pipeline Stage	E1	E2
Read	src2_l
	src2_h
Written	dst_l	dst_h
Unit in use	.S

Figure 4−18. Two-Cycle DP Instruction Phases

PG

PS PW

PR DP

DC

E1

E2

1 delay slot

4-24 Pipeline SPRU733