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Texas Instruments TMS320C67X/C67X+ DSP manual Nonmaskable Interrupt NMI

Models: TMS320C67X/C67X+ DSP

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Overview

5.1.1.2Nonmaskable Interrupt (NMI)

NMI is the second-highest priority interrupt and is generally used to alert the CPU of a serious hardware problem such as imminent power failure.

For NMI processing to occur, the nonmaskable interrupt enable (NMIE) bit in the interrupt enable register must be set to 1. If NMIE is set to 1, the only condi- tion that can prevent NMI processing is if the NMI occurs during the delay slots of a branch (whether the branch is taken or not).

NMIE is cleared to 0 at reset to prevent interruption of the reset. It is cleared at the occurrence of an NMI to prevent another NMI from being processed. You cannot manually clear NMIE, but you can set NMIE to allow nested NMIs. While NMI is cleared, all maskable interrupts (INT4−INT15) are disabled.

5.1.1.3Maskable Interrupts (INT4−INT15)

The CPUs of the C6000™ DSPs have 12 interrupts that are maskable. These have lower priority than the NMI and reset interrupts. These interrupts can be associated with external devices, on-chip peripherals, software control, or not be available.

Assuming that a maskable interrupt does not occur during the delay slots of a branch (this includes conditional branches that do not complete execution due to a false condition), the following conditions must be met to process a maskable interrupt:

-The global interrupt enable bit (GIE) bit in the control status register (CSR) is set to1.

-The NMIE bit in the interrupt enable register (IER) is set to1.

-The corresponding interrupt enable (IE) bit in the IER is set to1.

-The corresponding interrupt occurs, which sets the corresponding bit in the interrupt flags register (IFR) to 1 and there are no higher priority interrupt flag (IF) bits set in the IFR.

5-4

Interrupts

SPRU733

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Texas Instruments TMS320C67X/C67X+ DSP manual Nonmaskable Interrupt NMI

Contents

TMS320C67x/C67x+ DSP CPU and Instruction Set Reference Guide Copyright 2005, Texas Instruments Incorporated Read This First Trademarks Contents Instruction Set Contents Vii Mvkl Move Signed Constant Into Register Pipeline Interrupts SPRU733 Figures −18 Tables 131 Tables Examples Introduction TMS320C6000 DSP Family Overview TMS320 DSP Family OverviewInstrumentation Medical Military −1. Typical Applications for the TMS320 DSPsAutomotive Consumer Control General-Purpose Graphics/Imaging IndustrialTMS320C67x DSP Features and Options SPRU733 TMS320C67x DSP Features and Options TMS320C67x DSP Architecture −1. TMS320C67x DSP Block DiagramCentral Processing Unit CPU Internal MemoryMemory and Peripheral Options SPRU733 CPU Data Paths and Control General-Purpose Register Files Introduction−1. TMS320C67x CPU Data Paths Register Files Devices −1 -Bit/64-Bit Register Pairs−2. Functional Units and Operations Performed Functional UnitsMemory, Load, and Store Paths Register File Cross PathsAcronym Register Name Section Data Address PathsControl Register File −3. Control RegistersRegister Addresses for Accessing the Control Registers −4. Register Addresses for Accessing the Control RegistersAcronym Register Name Address Read/ Write Pipeline Stage Pipeline/Timing of Control Register AccessesAddressing Mode Register AMR −5. Addressing Mode Register AMR Field DescriptionsBit Field Value Description B6 Mode BK n Value Block Size −6. Block Size Calculations−4. Control Status Register CSR Control Status Register CSRBit Field −7. Control Status Register CSR Field DescriptionsDCC −8. Interrupt Clear Register ICR Field Descriptions Interrupt Clear Register ICR−9. Interrupt Enable Register IER Field Descriptions Interrupt Enable Register IER−10. Interrupt Flag Register IFR Field Descriptions Interrupt Flag Register IFR−9. Interrupt Return Pointer Register IRP Interrupt Return Pointer Register IRP−11. Interrupt Set Register ISR Field Descriptions Interrupt Set Register ISR−11.Interrupt Service Table Pointer Register Istp Interrupt Service Table Pointer Register IstpNonmaskable Interrupt NMI Return Pointer Register NRP 12 E1 Phase Program Counter PCE1Floating-Point Adder Configuration Register Fadcr Control Register File Extensions−13. Control Register File Extensions −14. Floating-Point Adder Configuration Register Fadcr NAN2 Inexact results status for .L1 −15. Floating-Point Auxiliary Configuration Register Faucr Floating-Point Auxiliary Configuration Register FaucrUND NaN select for .S2 src2 Signed infinity for .S1 −16. Floating-Point Multiplier Configuration Register Fmcr Floating-Point Multiplier Configuration Register FmcrInexact results status for .M2 Rounding mode select for .M1 Denormalized number select for .M1 src1 Topic Instruction SetSymbol Meaning Instruction Operation and Execution Notations−1. Instruction Operation and Execution Notations Rotl Occurs Extu l,r Greater than −2. Instruction Syntax and Opcode Notations Instruction Syntax and Opcode NotationsUcstn Bit unsigned constant field Ucst n SPRU733 Sdfpn −3. Ieee Floating-Point Notations−4. Special Single-Precision Values Symbol Sign s Exponent e Fraction f−2. Double-Precision Floating-Point Fields Symbol Hex Value Decimal Value−6. Special Double-Precision Values Delay Slots Instruction Type Slots Unit Latency Read Cycles† −8. Delay Slot and Functional Unit Latency−3. Basic Format of a Fetch Packet Parallel OperationsInstructions Example 3−1. Fully Serial p-Bit Pattern in a Fetch PacketExample 3−2. Fully Parallel p-Bit Pattern in a Fetch Packet Cycle/ExecuteExample Parallel Code Branching Into the Middle of an Execute PacketCycle/Execute Packet Instructions Conditional Bit Register Conditional Operations−9. Registers That Can Be Tested by Conditional Operations SpecifiedResource Constraints Constraints on Instructions Using the Same Functional UnitConstraints on Cross Paths 1X Following execute packets are valid Constraints on Loads and StoresFollowing code sequence is invalid Constraints on Long 40-Bit DataConstraints on Register Reads However, this code sequence is valid Constraints on Register WritesMPYSP2DP Constraints on Floating-Point InstructionsIntdp Tional unit on cycle i + 4, i + 5, or i + Addsp Subsp Spint Sptrunc Intsp Mpysp Addressing Modes Linear Addressing ModeCycle after LDW Cycles after LDW Circular Addressing ModeExample 3−4. LDW Instruction in Circular Mode Before LDWCycle after Addah Example 3−5. Addah Instruction in Circular ModeSyntax for Load/Store Address Generation Before AddahAddressing Type Address Register Mode Field Syntax Modification Performed−10. Indirect Address Generation for Load/Store −11. Address Generator Options for Load/StoreInstruction Descriptions Instruction CompatibilityExample Way each instruction is describedOpcode map field used For operand type Unit Opfield Execution for .L1, .L2 and .S1, .S2 Opcodes Absolute Value With Saturation ABSPipeline StageE1 Read src2 Written dst Unit in use Before instruction Cycle after instruction ABSDP, AbsspBefore instruction Cycle after instructionAbsdp Absolute Value, Double-Precision Floating-PointBefore instruction Cycles after instruction ABS, AbsspPipeline Stage Read WrittenAbssp Absolute Value, Single-Precision Floating-PointABS, Absdp ADD Add Two Signed Integers Without SaturationADD Unit in use Or .D ADDDP, ADDK, ADDSP, ADDU, ADD2, SADD, SUBAdd Two Signed Integers Without Saturation ADD Add Using Byte Addressing Mode AddabADD, ADDAD, ADDAH, Addaw Add Using Byte Addressing Mode Addab Addad Add Using Doubleword Addressing ModeADD, ADDAB, ADDAH, Addaw Add Using Halfword Addressing Mode AddahADD, ADDAB, ADDAD, Addaw Add Using Halfword Addressing Mode Addah Add Using Word Addressing Mode AddawADD, ADDAB, ADDAD, Addah Add Using Word Addressing Mode Addaw Adddp Add Two Double-Precision Floating-Point ValuesAdd Two Double-Precision Floating-Point Values Adddp Unit in use Or .S ADD, ADDSP, ADDU, SubdpAdd Signed 16-Bit Constant to Register AddkPipeline StageE1 Read cst16 Written dst Unit in use Addsp Add Two Single-Precision Floating-Point ValuesAdd Two Single-Precision Floating-Point Values Addsp ADD, ADDDP, ADDU, Subsp Add Two Unsigned Integers Without Saturation AdduADD, SADD, Subu Addu Add Two Unsigned Integers Without Saturation ADD2 Add Two 16-Bit Integers on Upper and Lower Register HalvesADD, ADDU, SUB2 Bitwise OR, XOR Branch Using a Displacement Opcode map field used For operand type UnitS1, .S2 Cycle Program Counter Value Action Delay Slots ExampleXuint Branch Using a RegisterWritten Branch Taken Unit in use Target Instruction Pipeline Stage ReadBranch Using an Interrupt Return Pointer IRPXsint −15. Program Counter Values for B IRP Instruction NRP Branch Using NMI Return Pointer−16. Program Counter Values for B NRP Instruction CLR Clear a Bit FieldSET Execution PipelineClear a Bit Field CLR Cmpeq Compare for Equality, Signed IntegersCMPEQDP, CMPEQSP, CMPGT, Cmplt Cmpeqdp Compare for Equality, Double-Precision Floating-Point ValuesCmpeqdp .S1 Cmpeqsp Compare for Equality, Single-Precision Floating-Point ValuesCMPEQ, CMPEQDP, CMPGTSP, Cmpltsp Cmpgt Compare for Greater Than, Signed IntegersCMPEQ, CMPGTDP, CMPGTSP, CMPGTU, Cmplt Cmpgt .L1X Cmpgtdp Delay Slots Functional Unit Latency See Also Example Cmpgtsp CMPEQSP, CMPGT, CMPGTDP, CMPGTU, Cmpltsp Cmpgtu Compare for Greater Than, Unsigned IntegersCMPGT, CMPGTDP, CMPGTSP, Cmpltu Cmplt Compare for Less Than, Signed IntegersCmplt Compare for Less Than, Signed Integers Compare for Less Than, Signed Integers Cmplt Wise, 0 is written to dst CMPEQDP, CMPGTDP, CMPLT, CMPLTSP, Cmpltu Cmpltsp Cmpltsp .S1 A1,A2,A3 Cmpltu Compare for Less Than, Unsigned IntegersInstruction Type Single-cycle Delay Slots See Also Example Dpint Convert Double-Precision Floating-Point Value to IntegerExample DpintFloating-Point Value DpspDPINT, DPTRUNC, INTSP, Spdp With Truncation DptruncDPINT, DPSP, Sptrunc DptruncEXT Extract and Sign-Extend a Bit FieldIf cond src2 ext csta, cstb → dst else nop Extu Extu Extract and Zero-Extend a Bit FieldIf cond src2 extu csta, cstb → dst else nop EXT Multicycle NOP With No Termination Until Interrupt IdleIdle DPINT, INTDPU, INTSP, Intspu IntdpIntdp INTDP, INTSP, Intspu IntdpuIntdpu INTDP, INTDPU, Intspu IntspINTDP, INTDPU, Intsp IntspuLeft Shift LdbuRegister Offset −17. Data Types Supported by Ldbu InstructionLDH, LDW Before LDB Cycle after LDBCycles after LDB −18. Data Types Supported by Ldbu Instruction 15-Bit Offset Load Byte From Memory With a 15-Bit Unsigned Constant OffsetBefore LDB Cycle after LDB Pipeline Stage Read B14 / B15 WrittenOr Register Offset LddwExecution Pipeline Instruction Type LDB, LDH, LDW −19. Data Types Supported by Ldhu Instruction LdhuLDB, LDW Before LDH Cycle after LDHCycles after LDH Tion operates only on the .D2 unit −20. Data Types Supported by Ldhu Instruction 15-Bit Offset LDW LDB, LDDW, LDH Cycle after LDW LDW LDB, LDH Leftmost Bit Detection Lmbd→ dst Pipeline StageE1 E2 Read Multiply Signed 16 LSB y Signed 16 LSBMPY MPYU, MPYSU, MPYUS, SmpyMPY Multiply Signed 16 LSB x Signed 16 LSB Mpydp Multiply Two Double-Precision Floating-Point ValuesPipeline E10 Stage Read MPY, MpyspMPYHU, MPYHSU, MPYHUS, Smpyh Multiply Signed 16 MSB y Signed 16 MSBMpyh Multiply Signed 16 MSB x Signed 16 MSB Multiply Signed 16 MSB y Signed 16 LSB MpyhlMPYHLU, MPYHSLU, MPYHULS, Smpyhl Mpyhl Multiply Signed 16 MSB x Signed 16 LSB MPYHL, MPYHSLU, Mpyhuls Multiply Unsigned 16 MSB y Unsigned 16 LSBMpyhslu Multiply Signed 16 MSB y Unsigned 16 LSBMPYHL, MPYHLU, Mpyhuls MPYH, MPYHU, Mpyhus Multiply Signed 16 MSB y Unsigned 16 MSBMpyhu Multiply Unsigned 16 MSB y Unsigned 16 MSBMPYH, MPYHSU, Mpyhus Multiply Unsigned 16 MSB y Signed 16 LSB MpyhulsMPYHL, MPYHLU, Mpyhslu MPYH, MPYHU, Mpyhsu Multiply Unsigned 16 MSB y Signed 16 MSBMultiply 32-Bit y 32-Bit Into 32-Bit Result MpyiMpyi Mpyid Mpyid Multiply 32-Bit y 32-Bit Into 64-Bit ResultMpyid Multiply 32-Bit x 32-Bit Into 64-Bit Result Multiply Signed 16 LSB y Signed 16 MSB MpylhMPYLHU, MPYLSHU, MPYLUHS, Smpylh Mpylh Multiply Signed 16 LSB x Signed 16 MSB MPYLH, MPYLSHU, Mpyluhs Multiply Unsigned 16 LSB y Unsigned 16 MSBMpylshu Multiply Signed 16 LSB y Unsigned 16 MSBMPYLH, MPYLHU, Mpyluhs Multiply Unsigned 16 LSB y Signed 16 MSB MpyluhsMPYLH, MPYLHU, Mpylshu Mpysp Multiply Two Single-Precision Floating-Point ValuesMPY, MPYDP, MPYSP2DP MpyspMpyspdp MPY, MPYDP, MPYSP, MPYSP2DP MpyspdpMultiply Two Single-Precision Floating-Point Values for MPYSP2DPDouble-Precision Result MPYSP2DP Multiply Signed 16 LSB y Unsigned 16 LSB MpysuMPY, MPYU, Mpyus MPY, MPYSU, Mpyus Multiply Unsigned 16 LSB y Unsigned 16 LSBMultiply Unsigned 16 LSB x Unsigned 16 LSB Mpyu Mpyus Multiply Unsigned 16 LSB y Signed 16 LSBMPY, MPYU, Mpysu Multiply Unsigned 16 LSB x Signed 16 LSB Mpyus Move From Register to Register If cond 0 + src2 → dst MVC Move Between Control File and Register FileSrc2 → dst −21. Register Addresses for Accessing the Control Registers Move Signed Constant Into Register and Sign Extend MVKPipeline StageE1 Read Written dst Unit in use MVKH, MVKL, Mvklh MVKH/MVKLH Move 16-Bit Constant Into Upper Bits of RegisterIf you are loading the address of a label, use Mvkl Pipeline Stage Read Written MVK, MVKH, MvklhNEG NegateNo Operation NOPUcst4 None Cycle after ADD Before NOPCycle after NOP No operation ExecutesNorm Normalize IntegerExecution If cond Norm src → dst Else nop Pipeline Not Bitwise notBitwise or AND, XOR Src1 or src2 → dstRcpdp Double-Precision Floating-Point Reciprocal ApproximationRCPSP, Rsqrdp Rcpsp Single-Precision Floating-Point Reciprocal ApproximationRCPDP, Rsqrsp Rsqrdp If src2 is positive infinity, positive 0 is placed in dst Rsqrsp Rsqrsp .S1 Sadd Add Two Signed Integers With SaturationADD, Ssub Add Two Signed Integers With Saturation Sadd SAT Saturate a 40-Bit Integer to a 32-Bit IntegerSAT .L2 SET Set a Bit FieldCLR If cond src2 SET csta, cstb → dst else nopSET .S1 SHL Arithmetic Shift LeftSHR, Sshl SHR Arithmetic Shift RightSHL, Shru Shru Logical Shift RightSHL, SHR MPY, SMPYH, SMPYHL, Smpylh SmpyCSR MPYH, SMPY, SMPYHL, Smpylh SmpyhMPYHL, SMPY, SMPYH, Smpylh SmpyhlInstruction Set 223 MPYLH, SMPY, SMPYH, Smpyhl SmpylhInstruction Set 225 Spdp DPSP, INTDP, SPINT, Sptrunc Spint Convert Single-Precision Floating-Point Value to IntegerDPINT, INTSP, SPDP, Sptrunc SpintSptrunc DPTRUNC, SPDP, Spint SptruncSshl Shift Left With SaturationSshl .S1 Ssub Subtract Two Signed Integers With SaturationSUB STB Before Cycle after Instruction STH, STWStore Byte to Memory With a 15-Bit Unsigned Constant Offset Pipeline Stage Read B14 /B15 , src Written Unit in use STH Before STB, STWInstruction Cycles after STH Instruction Type Store Delay Slots See Also STW STB, STH Store Word to Memory With a 15-Bit Unsigned Constant Offset 248 SUB Subtract Two Signed Integers Without SaturationSrc1 − src2 → dst else nop Src2 − src1 → dst ADD, SSUB, SUBC, SUBDP, SUBSP, SUBU, SUB2 Subtract Using Byte Addressing Mode SubabSUB, SUBAH, Subaw BK0 = 3 → size = A5 in circular addressing mode using BK0 Subtract Using Halfword Addressing Mode SubahSUB, SUBAB, Subaw Subtract Using Word Addressing Mode SubawSUB, SUBAB, Subah Subtract Using Word Addressing Mode Subaw Subtract Conditionally and Shift-Used for Division SubcADD, SSUB, SUB, SUBDP, SUBSP, SUBU, SUB2 Subtract Conditionally and Shift−Used for Division Subc Subdp Subtract Two Double-Precision Floating-Point ValuesSubtract Two Double-Precision Floating-Point Values Subdp ADDDP, SUB, SUBSP, Subu Subsp Subtract Two Single-Precision Floating-Point ValuesSubsp Subtract Two Single-Precision Floating-Point Values ADDSP, SUB, SUBDP, Subu Subtract Two Unsigned Integers Without Saturation SubuADDU, SSUB, SUB, SUBC, SUBDP, SUBSP, SUB2 Subtract Two Unsigned Integers Without Saturation Subu Src1 and placed in the lower-half of dst SUB2ADD2, SSUB, SUB, SUBC, Subu XOR Bitwise Exclusive orAND, or Zero Zero a RegisterPipeline Fetch Pipeline Operation OverviewDecode −2. Fetch Phases of the Pipeline−3. Decode Phases of the Pipeline Execute −4. Execute Phases of the PipelineClock cycle Fetch Pipeline Operation Summary−1. Operations Occurring During Pipeline Phases Stage Phase Symbol During This Phase Completed Adddp −7. Pipeline Phases Block Diagram Example 4−1. Execute Packet in −7 Pipeline Execution of Instruction Types Delay slots Functional Unit latencyDP Compare Instruction Type Execution Phases Cycle DPADDDP/SUBDP Mpyi Mpyid Mpydp Instruction Type Execution PhasesInstruction Type Execution PhasesSingle-Cycle Instructions −3. Single-Cycle Instruction ExecutionUnit in use M, or .D −4 y 16-Bit Multiply Instruction Execution 2 16 y 16-Bit Multiply Instructions−5. Store Instruction Execution Store Instructions−13. Store Instruction Execution Block Diagram −6. Load Instruction Execution Load Instructions−15. Load Instruction Execution Block Diagram −7. Branch Instruction Execution Branch Instructions−17. Branch Instruction Execution Block Diagram −8. Two-Cycle DP Instruction Execution Two-Cycle DP InstructionsFour-Cycle Instructions −9. Four-Cycle Instruction ExecutionUnit in use Or .M −10. Intdp Instruction Execution Intdp Instruction−11. DP Compare Instruction Execution DP Compare Instructions−12. ADDDP/SUBDP Instruction Execution ADDDP/SUBDP Instructions−13. Mpyi Instruction Execution Mpyi InstructionMpyid Instruction −14. Mpyid Instruction ExecutionPipeline Stage E4 E5 E6 E7 E8 E9 E10 Read −15. Mpydp Instruction Execution Mpydp Instruction−16. Mpyspdp Instruction Execution Mpyspdp InstructionFunctional Unit Constraints MPYSP2DP Instruction−17. MPYSP2DP Instruction Execution Unit Constraints −18. Single-Cycle .S-Unit Instruction ConstraintsInstruction Execution −19. DP Compare .S-Unit Instruction Constraints −20 -Cycle DP .S-Unit Instruction Constraints −21. ADDSP/SUBSP .S-Unit Instruction Constraints −22. ADDDP/SUBDP .S-Unit Instruction Constraints −23. Branch .S-Unit Instruction Constraints −24 y 16 Multiply .M-Unit Instruction Constraints −25 -Cycle .M-Unit Instruction Constraints −26. Mpyi .M-Unit Instruction Constraints −27. Mpyid .M-Unit Instruction Constraints −28. Mpydp .M-Unit Instruction Constraints −29. Mpysp .M-Unit Instruction Constraints −30. Mpyspdp .M-Unit Instruction Constraints −31. MPYSP2DP .M-Unit Instruction Constraints −32. Single-Cycle .L-Unit Instruction Constraints −33 -Cycle .L-Unit Instruction Constraints −34. Intdp .L-Unit Instruction Constraints −35. ADDDP/SUBDP .L-Unit Instruction Constraints −36. Load .D-Unit Instruction Constraints Unit Instruction Constraints−37. Store .D-Unit Instruction Constraints −38. Single-Cycle .D-Unit Instruction Constraints Lddw Performance Considerations Pipeline Stall −29. Multicycle NOP in an Execute Packet Multicycle NOPsCycle # Pipeline Phase Branch TargetOperation −40. Program Memory Accesses Versus Data Load AccessesMemory Considerations Data Load+10 −32. Program and Data Memory StallsExample 4−2. Load From Memory Banks −33 -Bank Interleaved Memory−34 -Bank Interleaved Memory With Two Memory Spaces −41. Loads in Pipeline from Example 4−2Interrupts Overview Types of Interrupts and Signals UsedPriority Interrupt Name Interrupt Type −1. Interrupt PrioritiesNonmaskable Interrupt NMI Interrupt Acknowledgment Iack and Interrupt Number INUMn −1. Interrupt Service Table Interrupt Service Table IST−2. Interrupt Service Fetch Packet 1238h Interrupt Service Table Pointer Istp Example 5−1. Relocation of Interrupt Service TableSummary of Interrupt Control Registers −2. Interrupt Control RegistersAcronym Register Name Description Globally Enabling and Disabling Interrupts MVC CSR,B0 Enabling and Disabling Interrupts Individual Interrupt ControlStatus of Interrupts Setting and Clearing InterruptsReturning From Interrupt Servicing Example 5−8. Code to Return From NMIExample 5−9. Code to Return from a Maskable Interrupt Setting the Nonreset Interrupt Flag Conditions for Processing a Nonreset InterruptInterrupt Detection and Processing Isfp Actions Taken During Nonreset Interrupt Processing PS PW PR DP DC Setting the Reset Interrupt FlagActions Taken During Reset Interrupt Processing Pipeline Interaction General PerformanceSingle Assignment Programming Programming ConsiderationsNested Interrupts Example 5−11. Code Using Single AssignmentSTW Example 5−14. Manual Interrupt Processing Manual Interrupt ProcessingTraps Example 5−15. Code Sequence to Invoke a TrapExample 5−16. Code Sequence for Trap Return Instruction C62x DSP C64x DSP C67x DSP C67x+ DSP Instruction CompatibilityCmpltu Intsp Mpylh Rsqrdp Subab Functional Unit Instruction Table B−1. Functional Unit to Instruction MappingDisplacement Register Intdp Intdpu Intsp Intspu N n n n n n n n n n n n n STB memory SUB Subab Subah Subaw Subc Subdp Subsp Subu SUB2 XOR Zero Unit Instructions and Opcode Maps Table C−1. Instructions Executing in the .D Functional Unit Instructions Executing in the .D Functional UnitTable C−2. .D Unit Opcode Map Symbol Definitions Opcode Map Symbols and MeaningsSyntax Modification Performed Table C−3. Address Generator Options for Load/StoreFigure C−1 or 2 Sources Instruction Format 32-Bit Opcode MapsAppendix D Table D−1. Instructions Executing in the .L Functional Unit Instructions Executing in the .L Functional UnitTable D−2. .L Unit Opcode Map Symbol Definitions Figure D−1 or 2 Sources Instruction Format Appendix E Table E−1. Instructions Executing in the .M Functional Unit Instructions Executing in the .M Functional UnitTable E−2. .M Unit Opcode Map Symbol Definitions Figure E−1. Extended M-Unit with Compound Operations Appendix F Table F−1. Instructions Executing in the .S Functional Unit Instructions Executing in the .S Functional UnitTable F−2. .S Unit Opcode Map Symbol Definitions Figure F−1 or 2 Sources Instruction Format Figure F−7. Branch with NOP Constant Instruction Format No Unit Specified Instructions and Opcode Maps Table G−1. Instructions Executing With No Unit Specified Instructions Executing With No Unit SpecifiedFigure G−1. Loop Buffer Instruction Format Index Cmpeqdp Dpsp Index-4 Reset Index-6 Mpysu Unit No unit instructions Rsqrdp To memory with a 15-bit unsigned constant offset STB 260 Single-precision Subsp 263