Texas Instruments TMS320C67X/C67X+ DSP manual General Performance, Pipeline Interaction

Performance Considerations

5.5 Performance Considerations

The interaction of the C6000 CPU and sources of interrupts present perfor- mance issues for you to consider when you are developing your code.

5.5.1General Performance

-Overhead. Overhead for all CPU interrupts is 9 cycles. You can see this in Figure 5−4, where no new instructions are entering the E1 pipeline phase during CPU cycles 6 through 14.

-Latency. Interrupt latency is 13 cycles (21 cycles for RESET). In Figure 5−4, although the interrupt is active in cycle 2, execution of interrupt service code does not begin until cycle 15.

-Frequency. The logic clears the nonreset interrupt (IFm) on cycle 8, with any incoming interrupt having highest priority. Thus, an interrupt is can be recognized every second cycle. Also, because a low-to-high transition is necessary, an interrupt can occur only every second cycle. However, the frequency of interrupt processing depends on the time required for inter- rupt service and whether you reenable interrupts during processing, thereby allowing nested interrupts. Effectively, only two occurrences of a specific interrupt can be recognized in two cycles.

5.5.2Pipeline Interaction

Because the serial or parallel encoding of fetch packets does not affect the DC and subsequent phases of the pipeline, no conflicts between code parallelism and interrupts exist. There are three operations or conditions that can affect or are affected by interrupts:

-Branches. Nonreset interrupts are delayed, if any execute packets n through n + 4 in Figure 5−4 contain a branch or are in the delay slots of a branch.

-Memory stalls. Memory stalls delay interrupt processing, because they inherently extend CPU cycles.

-Multicycle NOPs. Multicycle NOPs (including the IDLE instruction) operate like other instructions when interrupted, except when an interrupt causes annulment of any but the first cycle of a multicycle NOP. In that case, the address of the next execute packet in the pipeline is saved in NRP or IRP. This prevents returning to an IDLE instruction or a multicycle NOP that was interrupted.

SPRU733 Interrupts 5-21