Texas Instruments TMS320C67X/C67X+ DSP manual Interrupt Set Register ISR

Control Register File

2.7.9Interrupt Set Register (ISR)

The interrupt set register (ISR) allows you to manually set the maskable inter- rupts (INT15−INT4) in the interrupt flag register (IFR). Writing a 1 to any of the bits in ISR causes the corresponding interrupt flag (IFn) to be set in IFR. Writ- ing a 0 to any bit in ISR has no effect. You cannot set any bit in ISR to affect NMI or reset. The ISR is shown in Figure 2−10 and described in Table 2−11.

Note:

Any write to ISR (by the MVC instruction) effectively has one delay slot because the results cannot be read (by the MVC instruction) in IFR until two cycles after the write to ISR.

Any write to the interrupt clear register (ICR) is ignored by a simultaneous write to the same bit in ISR.

Figure 2−10. Interrupt Set Register (ISR)

31													16
							Reserved
							R-0
15	14	13	12	11	10	9	8	7	6	5	4	3	0
IS15	IS14	IS13	IS12	IS11	IS10	IS9	IS8	IS7	IS6	IS5	IS4		Reserved
					W-0								R-0

Legend: R = Read only; W = Writeable by the MVC instruction; -n= value after reset

Table 2−11. Interrupt Set Register (ISR) Field Descriptions

Bit	Field	Value	Description
31−16	Reserved	0	Reserved. The reserved bit location is always read as 0. A value written to this
			field has no effect.
15−4	ISn		Interrupt set.
		0	Corresponding interrupt flag (IFn) in IFR is not set.
		1	Corresponding interrupt flag (IFn) in IFR is set.
3−0	Reserved	0	Reserved. The reserved bit location is always read as 0. A value written to this
			field has no effect.

2-20 CPU Data Paths and Control SPRU733