Pipeline Operation Overview

Figure 4−3(a) shows the decode phases in sequential order from left to right. Figure 4−3(b) shows a fetch packet that contains two execute packets as they are processed through the decode stage of the pipeline. The last six instruc- tions of the fetch packet (FP) are parallel and form an execute packet (EP). This EP is in the dispatch phase (DP) of the decode stage. The arrows indicate each instruction’s assigned functional unit for execution during the same cycle. The NOP instruction in the eighth slot of the FP is not dispatched to a functional unit because there is no execution associated with it.

The first two slots of the fetch packet (shaded below) represent an execute packet of two parallel instructions that were dispatched on the previous cycle. This execute packet contains two MPY instructions that are now in decode (DC) one cycle before execution. There are no instructions decoded for the .L,

.S, and .D functional units for the situation illustrated.

Figure 4−3. Decode Phases of the Pipeline

(a)

(b)

DP DC

Decode

32

32

32

32

32

32

32

32

 

 

 

ADD

ADD

STW

STW

ADDK

NOP

DP

MPYH

DC

MPYH

.L1

.S1

.M1

.D1

Functional

units

.D2

.M2

.S2

.L2

NOP is not dispatched to a functional unit.

4-4

Pipeline

SPRU733

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Image 336
Texas Instruments TMS320C67X/C67X+ DSP manual 3. Decode Phases of the Pipeline