Texas Instruments TMS320C67X/C67X+ DSP manual 4. Execute Phases of the Pipeline

Pipeline Operation Overview

4.1.3Execute

The execute portion of the pipeline is subdivided into ten phases (E1−E10), as compared to the five phases in a fixed-point pipeline. Different types of instructions require different numbers of these phases to complete their execution. These phases of the pipeline play an important role in your understanding the device state at CPU cycle boundaries. The execution of dif- ferent types of instructions in the pipeline is described in section 4.2, Pipeline Execution of Instruction Types. Figure 4−4(a) shows the execute phases of the pipeline in sequential order from left to right. Figure 4−4(b) shows the portion of the functional block diagram in which execution occurs.

Figure 4−4. Execute Phases of the Pipeline

(a)	E1	E2	E3	E4		E5		E6		E7		E8	E9	E10
(b)
Execute													E1
SADD		B			SMPY				STH						STH	SMPYH			SUB			SADD
.L1		.S1			.M1				.D1						.D2	.M2			.S2				.L2
15 14 13 12 11 10 9			8	7	6	5	4	3	2	1	0		32	15 14 13 12 11 10 9			8	7	6	5	4	3	2	1	0
Register file A					Data 1				32						32	Data 2					Register file B
								Data memory interface control
	32								16			16		16		16								32
								0	1		2	3	4	5	6	7
								8	9
	Data address 1															Data address 2
										Internal data memory
										(byte addressable)
SPRU733																				Pipeline					4-5