SHL Arithmetic Shift Left

 

 

 

Pipeline

 

 

 

 

 

Pipeline

E1

 

 

 

 

Stage

 

 

 

 

 

 

 

Read

src1, src2

 

 

Written

dst

 

 

Unit in use

.S

 

 

 

 

 

Instruction Type

Single-cycle

 

Delay Slots

0

 

See Also

SHR, SSHL

 

Example 1

SHL .S1

A0,4,A1

 

Before instruction

 

A0

 

 

 

29E3 D31Ch

 

A0

 

 

 

 

 

 

 

A1

xxxx xxxxh

 

A1

 

 

 

 

1 cycle after instruction

29E3 D31Ch

9E3D 31C0h

Example 2

SHL .S2

B0,B1,B2

Before instruction

1 cycle after instruction

B0

B1

B2

4197 51A5h

0000 0009h

xxxx xxxxh

B0

B1

B2

4197 51A5h

0000 0009h

2EA3 4A00h

Example 3

SHL .S2

B1:B0,B2,B3:B2

 

 

Before instruction

 

B1:B0

 

 

 

 

0000

0009h

4197 51A5h

 

 

 

 

 

 

 

 

 

 

 

B2

0000

0022h

 

 

 

 

 

 

 

 

 

 

B3:B2

xxxx xxxxh

xxxx xxxxh

 

 

 

 

 

 

1 cycle after instruction

 

 

 

 

 

B1:B0

0000

0009h

4197

51A5h

 

 

 

 

 

 

 

 

 

 

B2

0000

0000h

 

 

 

 

 

 

 

 

 

 

 

 

B3:B2

0000

0094h

0000

0000h

 

 

 

 

 

3-214

Instruction Set

SPRU733

Page 274
Image 274
Texas Instruments TMS320C67X/C67X+ DSP manual SHR, Sshl, Pipeline Stage Read