Texas Instruments TMS320C67X/C67X+ DSP manual 14. Mpyid Instruction Execution

Pipeline Execution of Instruction Types

4.2.12 MPYID Instruction

The MPYID instruction uses the E1 through E10 phases of the pipeline to complete its operations (see Table 4−14). The sources are read on cycles E1 through E4, the lower 32 bits of the result are written on E9, and the upper 32 bits of the result are written on E10. The MPYID instruction is executed on the .M unit. The functional unit latency for the MPYID instruction is 4. Figure 4−24 shows the fetch, decode, and execute phases of the pipeline that the MPYID instruction uses.

Table 4−14. MPYID Instruction Execution

Pipeline Stage	E1	E2	E3	E4 E5 E6 E7 E8 E9	E10
Read	src1	src1	src1	src1
	src2	src2	src2	src2
Written				dst_l	dst_h
Unit in use	.M	.M	.M	.M

Figure 4−24. MPYID Instruction Phases

PG PS PW PR DP DC E1

E2 E3 E4 E5

E6 E7

E8 E9 E10

9 delay slots

4-30 Pipeline SPRU733