Texas Instruments TMS320C67X/C67X+ DSP manual Pipeline Execution of Instruction Types

Pipeline Execution of Instruction Types

4.2 Pipeline Execution of Instruction Types

The pipeline operation of the C67x DSP instructions can be categorized into fourteen instruction types. Thirteen of these are shown in Table 4−2 (NOP is not included in the table), which is a mapping of operations occurring in each execution phase for the different instruction types. The delay slots and functional unit latency associated with each instruction type are listed in the bottom row. See section 3.7.8 for any instruction constraints.

Table 4−2. Execution Stage Length Description for Each Instruction Type

		Instruction Type
Execution
phases	Single Cycle	16 y 16 Multiply	Store	Load	Branch
E1	Compute result and	Read operands and	Compute address	Compute	Target code
	write to register	start computations		address	in PG‡
E2		Compute result and	Send address and	Send address to
		write to register	data to memory	memory
E3			Access memory	Access memory
E4				Send data back
				to CPU
E5				Write data into
				register
E6
E7
E8
E9
E10
Delay slots	0	1	0†	4†	5‡
Functional	1	1	1	1	1
unit latency

†See sections 4.2.3 And 4.2.4 for more information on execution and delay slots for stores and loads.

‡ See section 4.2.5 for more information on branches.

Notes: 1) This table assumes that the condition for each instruction is evaluated as true. If the condition is evaluated as false, the instruction does not write any results or have any pipeline operation after E1.

2) NOP is not shown and has no operation in any of the execution phases.

4-12 Pipeline SPRU733