Texas Instruments TMS320C67X/C67X+ DSP manual 1. Interrupt Priorities

Overview

Table 5−1. Interrupt Priorities

Priority	Interrupt Name	Interrupt Type
Highest	Reset	Reset
	NMI	Nonmaskable
	INT4	Maskable
	INT5	Maskable
	INT6	Maskable
	INT7	Maskable
	INT8	Maskable
	INT9	Maskable
	INT10	Maskable
	INT11	Maskable
	INT12	Maskable
	INT13	Maskable
	INT14	Maskable
Lowest	INT15	Maskable

5.1.1.1Reset (RESET)

Reset is the highest priority interrupt and is used to halt the CPU and return it to a known state. The reset interrupt is unique in a number of ways:

-RESET is an active-low signal. All other interrupts are active-high signals.

-RESET must be held low for 10 clock cycles before it goes high again to reinitialize the CPU properly.

-The instruction execution in progress is aborted and all registers are returned to their default states.

-The reset interrupt service fetch packet must be located at address 0.

-RESET is not affected by branches.

SPRU733 Interrupts 5-3