Texas Instruments TMS320C67X/C67X+ DSP manual Constraints on Register Writes

Resource Constraints

3.7.7Constraints on Register Writes

Two instructions cannot write to the same register on the same cycle. Two instructions with the same destination can be scheduled in parallel as long as they do not write to the destination register on the same cycle. For example, an MPY issued on cycle i followed by an ADD on cycle i + 1 cannot write to the same register because both instructions write a result on cycle i + 1. Therefore, the following code sequence is invalid unless a branch occurs after the MPY, causing the ADD not to be issued.

MPY .M1 A0, A1, A2

ADD .L1 A4, A5, A2

However, this code sequence is valid:

MPY .M1 A0, A1, A2

ADD .L1 A4, A5, A2

Figure 3−4 shows different multiple-write conflicts. For example, ADD and SUB in execute packet L1 write to the same register. This conflict is easily detectable.

MPY in packet L2 and ADD in packet L3 might both write to B2 simultaneously; however, if a branch instruction causes the execute packet after L2 to be something other than L3, a conflict would not occur. Thus, the potential conflict in L2 and L3 might not be detected by the assembler. The instructions in L4 do not constitute a write conflict because they are mutually exclusive. In contrast, because the instructions in L5 may or may not be mutually exclusive, the assembler cannot determine a conflict. If the pipeline does receive commands to perform multiple writes to the same register, the result is undefined.

Figure 3−4. Examples of the Detectability of Write Conflicts by the Assembler

L1: ADD.L2 B5,B6,B7 ; \ detectable, conflict

SUB.S2 B8,B9,B7 ; /

L2:		MPY.M2	B0,B1,B2 ; \ not detectable
L3:		ADD.L2	B3,B4,B2	; /
L4:[!B0]		ADD.L2	B5,B6,B7 ; \ detectable, no conflict
	[B0]	SUB.S2	B8,B9,B7	; /
L5:[!B1]		ADD.L2	B5,B6,B7 ; \ not detectable
	[B0]	SUB.S2	B8,B9,B7	; /

SPRU733 Instruction Set 3-25