Texas Instruments TMS320C67X/C67X+ DSP manual Rsqrdp

Index

PGIE bit	2-13
pipeline
decode stage			4-3
execute stage			4-5
execution		4-12
factors that provide programming flexibility									4-1
fetch stage 4-2
functional unit constraints							4-33
overview		4-2
performance considerations 4-56
phases	4-2
stages	4-2
summary		4-6
pipeline execution				4-12
pipeline operation
ADDDP instruction					4-28
branch instructions					4-22
DP compare instruction							4-27
four-cycle instructions						4-25
INTDP instruction					4-26
load instructions				4-20
MPYDP instruction					4-31
MPYI instruction				4-29
MPYID instruction					4-30
MPYSPDP instruction						4-32
MPYSP2DP instruction							4-33
multiple execute packets in a fetch packet									4-56
multiply instructions					4-17
one execute packet per fetch packet								4-6
single-cycle instructions							4-16
store instructions				4-18
SUBDP instruction					4-28
two-cycle DP instructions							4-24
pipeline phases
block diagram			4-10
used during memory accesses 4-60
PR pipeline phase				4-2
programming considerations, interrupts								5-22
PS pipeline phase				4-2
PW pipeline phase				4-2
PWRD bits		2-13

R

RCPDP instruction 3-197

RCPSP instruction 3-199

reciprocal approximation
double-precision floating-point (RCPDP)							3-197
single-precision floating-point (RCPSP)							3-199
square-root
double-precision floating-point
(RSQRDP)			3-201
single-precision floating-point
(RSQRSP)			3-203
register files
cross paths	2-6
data address paths			2-7
general-purpose 2-2
memory, load, and store paths					2-6
relationship to data paths				2-6
registers
addresses for accessing				2-8
addressing mode register (AMR)						2-10
control register file			2-7
control register file extensions					2-23
control status register (CSR)					2-13
E1 phase program counter (PCE1)						2-22
floating-point adder configuration register
(FADCR)	2-23
floating-point auxiliary configuration register
(FAUCR)	2-27
floating-point multiplier configuration register
(FMCR)	2-31
interrupt clear register (ICR) 2-16
interrupt enable register (IER)					2-17
interrupt flag register (IFR)				2-18
interrupt return pointer register (IRP) 2-19
interrupt service table pointer register
(ISTP) 2-21
interrupt set register (ISR)				2-20
NMI return pointer register (NRP)						2-22
read constraints		3-24
write constraints		3-25

related documentation from Texas Instruments iii

resource constraints		3-20
cross paths	3-21
floating-point instructions			3-26
on loads and stores 3-22
on long data	3-23
on register reads		3-24
on register writes		3-25
on the same functional unit writing in the same
instruction cycle		3-20
using the same functional unit 3-20
return from maskable interrupt			5-15
return from NMI	5-15

SPRU733 Index-9