Instruction Syntax and Opcode Notations

3.2 Instruction Syntax and Opcode Notations

Table 3−2 explains the syntaxes and opcode fields used in the instruction descriptions.

The C64x CPU 32-bit opcodes are mapped in Appendix C through Appendix G.

Table 3−2. Instruction Syntax and Opcode Notations

Symbol

Meaning

 

 

baseR

base address register

CC

 

creg

3-bit field specifying a conditional register, see section 3.6

cst

constant

csta

constant a

cstb

constant b

cstn

n-bit constant field

dst

destination

dstms

 

dw

doubleword; 0 = word, 1 = doubleword

iin

bit n of the constant ii

ld/st

load or store; 0 = store, 1 = load

mode

addressing mode, see section 3.8

offsetR

register offset

op

opfield; field within opcode that specifies a unique instruction

opn

bit n of the opfield

pparallel execution; 0 = next instruction is not executed in parallel, 1 = next instruction is executed in parallel

rLDDW instruction

rsv reserved

sside A or B for destination; 0 = side A, 1 = side B.

sc

scaling mode; 0 = nonscaled, offsetR/ucst5 is not shifted; 1 = scaled, offsetR/ucst5 is shifted

scstn

n-bit signed constant field

 

 

SPRU733

Instruction Set

3-7

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Texas Instruments TMS320C67X/C67X+ DSP manual 2. Instruction Syntax and Opcode Notations