Texas Instruments TMS320C67X/C67X+ DSP manual ADDDP, SUB, SUBSP, Subu, Pipeline Stage Read

SUBDP Subtract Two Double-Precision Floating-Point Values
Pipeline
	Pipeline	E1	E2	E3	E4	E5	E6	E7
	Stage
	Read	src1_l src1_h
		src2_l src2_h
	Written						dst_l	dst_h
	Unit in use	.L or .S	.L or .S

For the C67x CPU, if dst is used as the source for the ADDDP, CMPEQDP, CMPLTDP, CMPGTDP, MPYDP, or SUBDP instruction, the number of delay slots can be reduced by one, because these instructions read the lower word of the DP source one cycle before the upper word of the DP source.

For the C67x+ CPU, the low half of the result is written out one cycle earlier than the high half. If dst is used as the source for the ADDDP, CMPEQDP, CMPLTDP, CMPGTDP, MPYDP, MPYSPDP, MPYSP2DP, or SUBDP instruction, the number of delay slots can be reduced by one, because these instructions read the lower word of the DP source one cycle before the upper word of the DP source.

Instruction Type		ADDDP/SUBDP
Delay Slots		6
Functional Unit		2
Latency
See Also		ADDDP, SUB, SUBSP, SUBU
Example		SUBDP .L1X B1:B0,A3:A2,A5:A4
	Before instruction					7 cycles after instruction
B1:B0
	4021 3333h		3333 3333h	8.6	B1:B0	4021	3333h	3333	3333h	8.6
A3:A2	C004 0000h		0000 0000h	−2.5	A3:A2	C004	0000h	0000	0000h	−2.5
A5:A4	xxxx xxxxh		xxxx xxxxh		A5:A4	4026	3333h	3333	3333h	11.1

3-262 Instruction Set SPRU733