Texas Instruments TMS320C67X/C67X+ DSP manual Addsp Subsp Spint Sptrunc Intsp Mpysp

	Resource Constraints
MPYSPDP	A 4-cycle instruction cannot be scheduled on that func-
	tional unit on cycle i + 2 or i + 3.
	A MPYI instruction cannot be scheduled on that function-
	al unit on cycle i + 2 or i + 3.
	A MPYID instruction cannot be scheduled on that func-
	tional unit on cycle i + 2 or i + 3.
	A MPYDP instruction cannot be scheduled on that func-
	tional unit on cycle i + 2 or i + 3.
	A MPYSP2DP instruction cannot be scheduled on that
	functional unit on cycle i + 2 or i + 3.
	A multiply (16 ⋅ 16-bit) instruction cannot be scheduled
	on that functional unit on cycle i + 4 or i + 5 due to a write
	hazard on cycle i + 5 or i + 6, respectively.
MPYSP2DP	A multiply (16 ⋅ 16-bit) instruction cannot be scheduled
	on that functional unit on cycle i + 2 or i + 3 due to a write
	hazard on cycle i + 3 or i + 4, respectively.

All of the above cases deal with double-precision floating-point instructions or the MPYI or MPYID instructions except for the 4-cycle case. A 4-cycle instruc- tion consists of both single- and double-precision floating-point instructions. Therefore, the 4-cycle case is important for the following single-precision float- ing-point instructions:

-ADDSP

-SUBSP

-SPINT

-SPTRUNC

-INTSP

-MPYSP

The .S and .L units share their long write port with the load port for the 32 most significant bits of an LDDW load. Therefore, the LDDW instruction and the .S or .L unit writing a long result cannot write to the same register file on the same cycle. The LDDW writes to the register file on pipeline phase E5. Instructions that use a long result and use the .L and .S unit write to the register file on pipe- line phase E1. Therefore, the instruction with the long result must be sched- uled later than four cycles following the LDDW instruction if both instructions use the same side.

SPRU733 Instruction Set 3-29