Texas Instruments TMS320C67X/C67X+ DSP manual Pipeline/Timing of Control Register Accesses

Control Register File

2.7.2Pipeline/Timing of Control Register Accesses

All MVC instructions are single-cycle instructions that complete their access of the explicitly named registers in the E1 pipeline phase. This is true whether MVC is moving a general register to a control register, or conversely. In all cases, the source register content is read, moved through the .S2 unit, and written to the destination register in the E1 pipeline phase.

Pipeline Stage	E1
Read	src2
Written	dst
Unit in use	.S2

Even though MVC modifies the particular target control register in a single cycle, it can take extra clocks to complete modification of the non-explicitly named register. For example, the MVC cannot modify bits in the IFR directly. Instead, MVC can only write 1’s into the ISR or the ICR to specify setting or clearing, respectively, of the IFR bits. MVC completes this ISR/ICR write in a single (E1) cycle but the modification of the IFR bits occurs one clock later. For more information on the manipulation of ISR, ICR, and IFR, see section 2.7.9, section 2.7.5, and section 2.7.7.

Saturating instructions, such as SADD, set the saturation flag bit (SAT) in CSR indirectly. As a result, several of these instructions update the SAT bit one full clock cycle after their primary results are written to the register file. For exam- ple, the SMPY instruction writes its result at the end of pipeline stage E2; its primary result is available after one delay slot. In contrast, the SAT bit in CSR is updated one cycle later than the result is written; this update occurs after two delay slots. (For the specific behavior of an instruction, refer to the description of that individual instruction).

The B IRP and B NRP instructions directly update the GIE and NMIE, respectively. Because these branches directly modify CSR and IER, respectively, there are no delay slots between when the branch is issued and when the control register updates take effect.

SPRU733 CPU Data Paths and Control 2-9