Adddp | Texas Instruments TMS320C67X/C67X+ DSP instruction

Pipeline Operation Overview

†This assumes that the conditions for the instructions are evaluated as true. If the condition is evaluated as false, the instruction does not write an y results or have any pipeline operation after E1.

Figure 4−7 shows a functional block diagram of the pipeline stages. The pipe- line operation is based on CPU cycles. A CPU cycle is the period during which a particular execute packet is in a particular pipeline phase. CPU cycle bound- aries always occur at clock cycle boundaries.

As code flows through the pipeline phases, it is processed by different parts of the C67x DSP. Figure 4−7 shows a full pipeline with a fetch packet in every phase of fetch. One execute packet of eight instructions is being dispatched at the same time that a 7-instruction execute packet is in decode. The arrows between DP and DC correspond to the functional units identified in the code in Example 4−1.

In the DC phase portion of Figure 4−7, one box is empty because a NOP was the eighth instruction in the fetch packet in DC, and no functional unit is needed for a NOP. Finally, Figure 4−7 shows six functional units processing code during the same cycle of the pipeline.

Pipeline

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Texas Instruments TMS320C67X/C67X+ DSP manual Adddp

Models: TMS320C67X/C67X+ DSP

ADDDP/

Figure 4−7 shows a functional block diagram of the pipeline stages. The pipe- line operation is based on CPU cycles. A CPU cycle is the period during which a particular execute packet is in a particular pipeline phase. CPU cycle bound- aries always occur at clock cycle boundaries.

In the DC phase portion of Figure 4−7, one box is empty because a NOP was the eighth instruction in the fetch packet in DC, and no functional unit is needed for a NOP. Finally, Figure 4−7 shows six functional units processing code during the same cycle of the pipeline.