Texas Instruments TMS320C67X/C67X+ DSP

Control Register File Extensions

CPU Data Paths and Control2-28 SPRU733

Table 2−15. Floating-Point Auxiliary Configuration Register (FAUCR)

Field Descriptions (Continued)

Bit DescriptionValueField

25 UNORD Source to a compare operation for .S2

0 NaN is not a source to a compare operation.

1 NaN is a source to a compare operation.

24 UND Result underflow status for .S2.

0 Result does not underflow.

1 Result underflows.

23 INEX Inexact results status for .S2.

1 Result differs from what would have been computed had the exponent range

and precision been unbounded; never set with INVAL.

22 OVER Result overflow status for .S2.

0 Result does not overflow.

1 Result overflows.

21 INFO Signed infinity for .S2.

0 Result is not signed infinity.

1 Result is signed infinity.

20 INVAL

0 A signed NaN (SNaN) is not a source.

1 A signed NaN (SNaN) is a source. NaN is a source in a floating-point to integer

conversion or when infinity is subtracted from infinity.

19 DEN2 Denormalized number select for .S2 src2.

0src2 is not a denormalized number.

1src2 is a denormalized number.

18 DEN1 Denormalized number select for .S2 src1.

0src1 is not a denormalized number.

1src1 is a denormalized number.

Contents

Main Copyright 2005, Texas Instruments Incorporated Preface Read This First About This Manual Notational Conventions Related Documentation From Texas Instruments Trademarks Contents Page Page Page Page Page Page Figures Page Tables Page Page Examples a Chapter 1 Introduction 1.1 TMS320 DSP Family Overview 1.2 TMS320C6000 DSP Family Overview Table 11. Typical Applications for the TMS320 DSPs 1.3 TMS320C67x DSP Features and Options Page Page TMS320C67x DSP Architecture 1-7IntroductionSPRU733 1.4 TMS320C67x DSP Architecture Figure 11. TMS320C67x DSP Block Diagram C6000 CPU 1.4.1 Central Processing Unit (CPU) 1.4.2 Internal Memory 1.4.3 Memory and Peripheral Options Page CPU Data Paths and Control Chapter 2 2.1 Introduction 2.2 General-Purpose Register Files General-Purpose Register Files 2-3CPU Data Paths and ControlSPRU733 Figure 21. TMS320C67x CPU Data Paths Data path B Data path A Table 21. 40-Bit/64-Bit Register Pairs Figure 22. Storage Scheme for 40-Bit Data in a Register Pair 2.3 Functional Units Table 22. Functional Units and Operations Performed 2.4 Register File Cross Paths 2.5 Memory, Load, and Store Paths 2.6 Data Address Paths 2.7 Control Register File Table 23. Control Registers 2.7.1 Register Addresses for Accessing the Control Registers Table 24. Register Addresses for Accessing the Control Registers 2.7.2 Pipeline/Timing of Control Register Accesses 2.7.3 Addressing Mode Register (AMR) Figure 23. Addressing Mode Register (AMR) Table 25. Addressing Mode Register (AMR) Field Descriptions Page Table 25. Addressing Mode Register (AMR) Field Descriptions (Continued) Table 26. Block Size Calculations 2.7.4 Control Status Register (CSR) Figure 24. Control Status Register (CSR) Figure 25. PWRD Field of Control Status Register (CSR) Table 27. Control Status Register (CSR) Field Descriptions Table 27. Control Status Register (CSR) Field Descriptions (Continued) 2.7.5 Interrupt Clear Register (ICR) Figure 26. Interrupt Clear Register (ICR) Table 28. Interrupt Clear Register (ICR) Field Descriptions 2.7.6 Interrupt Enable Register (IER) Figure 27. Interrupt Enable Register (IER) Table 29. Interrupt Enable Register (IER) Field Descriptions 2.7.7 Interrupt Flag Register (IFR) Figure 28. Interrupt Flag Register (IFR) Table 210. Interrupt Flag Register (IFR) Field Descriptions 2.7.8 Interrupt Return Pointer Register (IRP) Figure 29. Interrupt Return Pointer Register (IRP) 2.7.9 Interrupt Set Register (ISR) Figure 210. Interrupt Set Register (ISR) Table 211. Interrupt Set Register (ISR) Field Descriptions 2.7.10 Interrupt Service Table Pointer Register (ISTP) Figure 211.Interrupt Service Table Pointer Register (ISTP) Table 212. Interrupt Service Table Pointer Register (ISTP) Field Descriptions 2.7.11 Nonmaskable Interrupt (NMI) Return Pointer Register (NRP) Figure 212. NMI Return Pointer Register (NRP) 2.7.12 E1 Phase Program Counter (PCE1) Figure 213. E1 Phase Program Counter (PCE1) 2.8 Control Register File Extensions Table 213. Control Register File Extensions 2.8.1 Floating-Point Adder Configuration Register (FADCR) Figure 214. Floating-Point Adder Configuration Register (FADCR) Field Descriptions Page Page 2.8.2 Floating-Point Auxiliary Configuration Register (FAUCR) Figure 215. Floating-Point Auxiliary Configuration Register (FAUCR) Field Descriptions Page Page Page 2.8.3 Floating-Point Multiplier Configuration Register (FMCR) Figure 216. Floating-Point Multiplier Configuration Register (FMCR) Field Descriptions Page Page Page Instruction Set Chapter 3 3.1 Instruction Operation and Execution Notations Table 31 explains the symbols used in the instruction descriptions. Table 31. Instruction Operation and Execution Notations Page Page Page Page 3.2 Instruction Syntax and Opcode Notations Table 32. Instruction Syntax and Opcode Notations Table 32. Instruction Syntax and Opcode Notations (Continued) 3.3 Overview of IEEE Standard Single- and Double-Precision Formats Table 33. IEEE Floating-Point Notations Figure 31. Single-Precision Floating-Point Fields Table 34. Special Single-Precision Values Table 35. Hexadecimal and Decimal Representation for Selected Single-Precision Values Figure 32. Double-Precision Floating-Point Fields Table 36. Special Double-Precision Values Table 37. Hexadecimal and Decimal Representation for Selected Double-Precision Values 3.4 Delay Slots Table 38. Delay Slot and Functional Unit Latency 3.5 Parallel Operations Figure 33. Basic Format of a Fetch Packet Example 31. Fully Serial p-Bit Pattern in a Fetch Packet This p-bit pattern: All eight instructions are executed in parallel. results in this execution sequence: The eight instructions are executed sequentially. Example 33. Partially Serial p-Bit Pattern in a Fetch Packet 3.5.1 Example Parallel Code 3.5.2 Branching Into the Middle of an Execute Packet 3.6 Conditional Operations Table 39. Registers That Can Be Tested by Conditional Operations 3.7 Resource Constraints 3.7.1 Constraints on Instructions Using the Same Functional Unit 3.7.2 Constraints on the Same Functional Unit Writing in the Same Instruction Cycle 3.7.3 Constraints on Cross Paths (1X and 2X) 3.7.4 Constraints on Loads and Stores 3.7.5 Constraints on Long (40-Bit) Data 3.7.6 Constraints on Register Reads 3.7.7 Constraints on Register Writes Figure 34. Examples of the Detectability of Write Conflicts by the Assembler 3.7.8 Constraints on Floating-Point Instructions Page Page Page 3.8 Addressing Modes 3.8.1 Linear Addressing Mode 3.8.2 Circular Addressing Mode Example 34. LDW Instruction in Circular Mode Example 35. ADDAH Instruction in Circular Mode 3.8.3 Syntax for Load/Store Address Generation Table 310. Indirect Address Generation for Load/Store Table 311. Address Generator Options for Load/Store 3.9 Instruction Compatibility 3.10 Instruction Descriptions The way each instruction is described. Example Page ABS Absolute Value With Saturation ABS Page ABSDP Absolute Value, Double-Precision Floating-Point ABSDP Page ABSSP Absolute Value, Single-Precision Floating-Point ABSSP Page ADD Add Two Signed Integers Without Saturation Syntax ADD (.unit) src1, src2, dst or ADD (.D1 or .D2) src2, src1, dst Page ADD Example 1 Example 2 Example 3 Example 4 ADDAB Add Using Byte Addressing Mode ADDAB Page ADDAD Add Using Doubleword Addressing Mode ADDAD Page ADDAH Add Using Halfword Addressing Mode ADDAH Page ADDAW Add Using Word Addressing Mode ADDAW Page ADDDP Add Two Double-Precision Floating-Point Values ADDDP Page ADDDP Add Signed 16-Bit Constant to Register ADDK ADDSP Add Two Single-Precision Floating-Point Values ADDSP Page ADDSP Add Two Unsigned Integers Without Saturation ADDU ADDU Example 1 Example 2 Add Two 16-Bit Integers on Upper and Lower Register Halves ADD2 ADD2 Bitwise AND AND Syntax AND (.unit) src1, src2, dst AND Branch Using a Displacement B Example Table 313 gives the program counter values and actions for the following code example. Table 313. Program Counter Values for Example Branch Using a Displacement Branch Using a Register B Table 314. Program Counter Values for Example Branch Using a Register Branch Using an Interrupt Return Pointer B IRP B IRP Table 315. Program Counter Values for B IRP Instruction Branch Using NMI Return Pointer B NRP B NRP Table 316. Program Counter Values for B NRP Instruction Clear a Bit Field CLR Page CMPEQ Compare for Equality, Signed Integers CMPEQ Page CMPEQDP Compare for Equality, Double-Precision Floating-Point Values CMPEQDP Page CMPEQSP Compare for Equality, Single-Precision Floating-Point Values CMPEQSP Page CMPGT Compare for Greater Than, Signed Integers CMPGT Syntax CMPGT (.unit) src1, src2, dst .unit = .L1 or .L2 Page CMPGT Example 1 Example 2 Example 3 Example 4 Compare for Greater Than, Double-Precision Floating-Point Values CMPGTDP CMPGTDP Compare for Greater Than, Single-Precision Floating-Point Values CMPGTSP CMPGTSP Compare for Greater Than, Unsigned Integers CMPGTU CMPGTU Compare for Less Than, Signed Integers Syntax CMPLT (.unit) src1, src2, dst .unit = .L1 or .L2 CMPLT Example 1 Example 2 Example 3 CMPLTDP Compare for Less Than, Double-Precision Floating-Point Values CMPLTDP Page CMPLTSP Compare for Less Than, Single-Precision Floating-Point Values CMPLTSP Page CMPLTU Compare for Less Than, Unsigned Integers CMPLTU Instruction Type Single-cycle Delay Slots 0 See Also CMPGTU, CMPLT, CMPLTDP, CMPLTSP Example 1 Example 2 Example 3 DPINT Convert Double-Precision Floating-Point Value to Integer DPINT Page DPSP Convert Double-Precision Floating-Point Value to Single-Precision DPSP Page DPTRUNC Convert Double-Precision Floating-Point Value to Integer With Truncation DPTRUNC Page EXT Extract and Sign-Extend a Bit Field EXT Page EXT Extract and Zero-Extend a Bit Field EXTU Page Page Convert Signed Integer to Double-Precision Floating-Point Value INTDP Page Convert Unsigned Integer to Double-Precision Floating-Point Value INTDPU Page Convert Signed Integer to Single-Precision Floating-Point Value INTSP INTSPU Convert Unsigned Integer to Single-Precision Floating-Point Value INTSPU Load Byte From Memory With a 5-Bit Unsigned Constant Offset or Table 317. Data Types Supported by LDB(U) Instruction LDB(U) Example Load Byte From Memory With a 15-Bit Unsigned Constant Offset Table 318. Data Types Supported by LDB(U) Instruction (15-Bit Offset) Page LDDW Load Doubleword From Memory With an Unsigned Constant Offset or Register Offset LDDW Page LDDW Load Halfword From Memory With a 5-Bit Unsigned Constant Offset or Register Offset Table 319. Data Types Supported by LDH(U) Instruction LDH(U) Example Load Halfword From Memory With a 15-Bit Unsigned Constant Offset Table 320. Data Types Supported by LDH(U) Instruction (15-Bit Offset) LDW Load Word From Memory With a 5-Bit Unsigned Constant Offset or Page LDW Example 1 Example 2 Example 3 Load Word From Memory With a 15-Bit Unsigned Constant Offset LDW Leftmost Bit Detection LMBD LMBD Multiply Signed 16 LSB Signed 16 LSB MPY MPY Example 1 Example 2 Multiply Two Double-Precision Floating-Point Values MPYDP MPYDP Multiply Signed 16 MSB Signed 16 MSB MPYH MPYH Example Multiply Signed 16 MSB Signed 16 LSB MPYHL MPYHL Example Multiply Unsigned 16 MSB Unsigned 16 LSB MPYHLU MPYHSLU Multiply Signed 16 MSB Unsigned 16 LSB MPYHSLU Multiply Signed 16 MSB Unsigned 16 MSB MPYHSU MPYHU Multiply Unsigned 16 MSB Unsigned 16 MSB MPYHU Multiply Unsigned 16 MSB Signed 16 LSB MPYHULS MPYHUS Multiply Unsigned 16 MSB Signed 16 MSB MPYHUS Multiply 32-Bit 32-Bit Into 32-Bit Result MPYI MPYI Multiply 32-Bit 32-Bit Into 64-Bit Result MPYID MPYID Multiply Signed 16 LSB Signed 16 MSB MPYLH MPYLH Example Multiply Unsigned 16 LSB Unsigned 16 MSB MPYLHU MPYLSHU Multiply Signed 16 LSB Unsigned 16 MSB MPYLSHU Multiply Unsigned 16 LSB Signed 16 MSB MPYLUHS MPYSP Multiply Two Single-Precision Floating-Point Values MPYSP Page MPYSPDP Multiply Single-Precision Floating-Point Value Double-Precision MPYSPDP Page MPYSP2DP Multiply Two Single-Precision Floating-Point Values for Double-Precision Result MPYSP2DP Page MPYSU Multiply Signed 16 LSB Unsigned 16 LSB MPYSU Page MPYU Multiply Unsigned 16 LSB Unsigned 16 LSB MPYU Example MPYUS Multiply Unsigned 16 LSB Signed 16 LSB MPYUS Example MV Move From Register to Register MV Syntax MV (.unit) src2, dst .unit = .L1, .L2, .S1, .S2, .D1, .D2 Page MVC Move Between Control File and Register File MVC Page MVC Table 321. Register Addresses for Accessing the Control Registers Move Signed Constant Into Register and Sign Extend MVK MVK Move 16-Bit Constant Into Upper Bits of Register MVKH/MVKLH MVKH/MVKLH Move Signed Constant Into Register and Sign Extend MVKL MVKL Negate NEG NOP No Operation NOP Example 1 Example 2 NORM Normalize Integer NORM Page NOT Bitwise NOT NOT Bitwise OR OR Syntax OR (.unit) src1, src2, dst OR Double-Precision Floating-Point Reciprocal Approximation RCPDP RCPDP Single-Precision Floating-Point Reciprocal Approximation RCPSP RCPSP Double-Precision Floating-Point Square-Root Reciprocal Approximation RSQRDP RSQRDP Single-Precision Floating-Point Square-Root Reciprocal Approximation RSQRSP RSQRSP Add Two Signed Integers With Saturation SADD Example 3 SAT Saturate a 40-Bit Integer to a 32-Bit Integer SAT Example 1 Example 2 Example 3 SET Set a Bit Field SET Page SET Arithmetic Shift Left SHL Syntax SHL (.unit) src2, src1, dst .unit = .S1 or .S2 SHL Arithmetic Shift Right SHR SHR Logical Shift Right SHRU SHRU Multiply Signed 16 LSB Signed 16 LSB With Left Shift and Saturation SMPY SMPY Example Multiply Signed 16 MSB Signed 16 MSB With Left Shift and Saturation SMPYH SMPYHL Multiply Signed 16 MSB Signed 16 LSB With Left Shift and Saturation SMPYHL Example SMPYLH Multiply Signed 16 LSB Signed 16 MSB With Left Shift and Saturation SMPYLH Example SPDP Convert Single-Precision Floating-Point Value to Double-Precision SPDP Page SPINT Convert Single-Precision Floating-Point Value to Integer SPINT Page SPTRUNC Convert Single-Precision Floating-Point Value to Integer With Truncation SPTRUNC Page SSHL Shift Left With Saturation SSHL Page SSUB Subtract Two Signed Integers With Saturation SSUB Page STB Store Byte to Memory With a 5-Bit Unsigned Constant Offset or Page STB Store Byte to Memory With a 15-Bit Unsigned Constant Offset Page STH Store Halfword to Memory With a 5-Bit Unsigned Constant Offset or Page STH Example 2 Store Halfword to Memory With a 15-Bit Unsigned Constant Offset STH Store Word to Memory With a 5-Bit Unsigned Constant Offset or STW Store Word to Memory With a 15-Bit Unsigned Constant Offset STW Subtract Two Signed Integers Without Saturation Syntax SUB (.unit) src1, src2, dst or SUB (.D1 or .D2) src2, src1, dst Page Page SUB Subtract Using Byte Addressing Mode SUBAB SUBAB Example Subtract Using Halfword Addressing Mode SUBAH SUBAW Subtract Using Word Addressing Mode SUBAW Example SUBC Subtract Conditionally and ShiftUsed for Division SUBC Page SUBDP Subtract Two Double-Precision Floating-Point Values SUBDP Page SUBDP Subtract Two Single-Precision Floating-Point Values SUBSP Page SUBU Subtract Two Unsigned Integers Without Saturation SUBU Example SUB2 Subtract Two 16-Bit Integers on Upper and Lower Register Halves SUB2 Page XOR Bitwise Exclusive OR XOR Syntax XOR (.unit) src1, src2, dst .unit = .L1, .L2, .S1, .S2 Page ZERO Zero a Register ZERO Pipeline Chapter 4 4.1 Pipeline Operation Overview Figure 41. Pipeline Stages 4.1.1 Fetch Figure 42. Fetch Phases of the Pipeline 4.1.2 Decode The decode phases of the pipeline are: Figure 43. Decode Phases of the Pipeline 4.1.3 Execute Figure 44. Execute Phases of the Pipeline 4.1.4 Pipeline Operation Summary Figure 45. Pipeline Phases Figure 46. Pipeline Operation: One Execute Packet per Fetch Packet Table 41. Operations Occurring During Pipeline Phases Page Table 41. Operations Occurring During Pipeline Phases (Continued) Figure 47. Pipeline Phases Block Diagram Example 41. Execute Packet in Figure 47 4.2 Pipeline Execution of Instruction Types Table 42. Execution Stage Length Description for Each Instruction Type Page Page Page 4.2.1 Single-Cycle Instructions Table 43. Single-Cycle Instruction Execution Figure 48. Single-Cycle Instruction Phases Figure 49. Single-Cycle Instruction Execution Block Diagram 4.2.2 16 y 16-Bit Multiply Instructions Table 44. 16 16-Bit Multiply Instruction Execution Figure 410. Multiply Instruction Phases Figure 411.Multiply Instruction Execution Block Diagram 4.2.3 Store Instructions Table 45. Store Instruction Execution Figure 412. Store Instruction Phases Figure 413. Store Instruction Execution Block Diagram 4.2.4 Load Instructions Table 46. Load Instruction Execution Figure 414. Load Instruction Phases Figure 415. Load Instruction Execution Block Diagram 4.2.5 Branch Instructions Table 47. Branch Instruction Execution Figure 416. Branch Instruction Phases Figure 417. Branch Instruction Execution Block Diagram 4.2.6 Two-Cycle DP Instructions Table 48. Two-Cycle DP Instruction Execution Figure 418. Two-Cycle DP Instruction Phases 4.2.7 Four-Cycle Instructions Table 49. Four-Cycle Instruction Execution Figure 419. Four-Cycle Instruction Phases Page 4.2.9 DP Compare Instructions Table 411. DP Compare Instruction Execution Figure 421. DP Compare Instruction Phases 4.2.10 ADDDP/SUBDP Instructions Table 412. ADDDP/SUBDP Instruction Execution Figure 422. ADDDP/SUBDP Instruction Phases 4.2.11 MPYI Instruction Table 413. MPYI Instruction Execution Figure 423. MPYI Instruction Phases 4.2.12 MPYID Instruction Table 414. MPYID Instruction Execution Figure 424. MPYID Instruction Phases 4.2.13 MPYDP Instruction Table 415. MPYDP Instruction Execution Figure 425. MPYDP Instruction Phases 4.2.14 MPYSPDP Instruction Table 416. MPYSPDP Instruction Execution Figure 426. MPYSPDP Instruction Phases 4.2.15 MPYSP2DP Instruction Table 417. MPYSP2DP Instruction Execution 4.3 Functional Unit Constraints 4.3.1 .S-Unit Constraints Table 418 shows the instruction constraints for single-cycle instructions Table 418. Single-Cycle .S-Unit Instruction Constraints Table 419 shows the instruction constraints for DP compare instructions Table 419. DP Compare .S-Unit Instruction Constraints Table 420 shows the instruction constraints for 2-cycle DP instructions exe- cuting on the .S unit. Table 420. 2-Cycle DP .S-Unit Instruction Constraints Table 421 shows the instruction constraints for ADDSP/SUBSP instructions Table 421. ADDSP/SUBSP .S-Unit Instruction Constraints Table 422 shows the instruction constraints for ADDDP/SUBDP instructions Table 422. ADDDP/SUBDP .S-Unit Instruction Constraints Table 423 shows the instruction constraints for branch instructions executing on the .S unit. Table 423. Branch .S-Unit Instruction Constraints 4.3.2 .M-Unit Constraints Table 424 shows the instruction constraints for 16 16 multiply instructions Table 424. 16 16 Multiply .M-Unit Instruction Constraints Table 425 shows the instruction constraints for 4-cycle instructions executing Table 425. 4-Cycle .M-Unit Instruction Constraints Table 426 shows the instruction constraints for MPYI instructions executing Table 426. MPYI .M-Unit Instruction Constraints Table 427 shows the instruction constraints for MPYID instructions executing Table 427. MPYID .M-Unit Instruction Constraints Table 428 shows the instruction constraints for MPYDP instructions Table 428. MPYDP .M-Unit Instruction Constraints Table 429 shows the instruction constraints for MPYSP instructions Table 429. MPYSP .M-Unit Instruction Constraints Table 430 shows the instruction constraints for MPYSPDP instructions Table 430. MPYSPDP .M-Unit Instruction Constraints Table 431 shows the instruction constraints for MPYSP2DP instructions Table 431. MPYSP2DP .M-Unit Instruction Constraints 4.3.3 .L-Unit Constraints Table 432 shows the instruction constraints for single-cycle instructions executing on the .L unit. Table 432. Single-Cycle .L-Unit Instruction Constraints Table 433 shows the instruction constraints for 4-cycle instructions executing on the .L unit. Table 433. 4-Cycle .L-Unit Instruction Constraints Table 434 shows the instruction constraints for INTDP instructions executing on the .L unit. Table 434. INTDP .L-Unit Instruction Constraints Table 435 shows the instruction constraints for ADDDP/SUBDP instructions executing on the .L unit. Table 435. ADDDP/SUBDP .L-Unit Instruction Constraints 4.3.4 .D-Unit Instruction Constraints Table 436 shows the instruction constraints for load instructions executing on the .D unit. Table 436. Load .D-Unit Instruction Constraints Table 437 shows the instruction constraints for store instructions executing on the .D unit. Table 437. Store .D-Unit Instruction Constraints Table 438 shows the instruction constraints for single-cycle instructions executing on the .D unit. Table 438. Single-Cycle .D-Unit Instruction Constraints Table 439. LDDW Instruction With Long Write Instruction Constraints 4.4 Performance Considerations 4.4.1 Pipeline Operation With Multiple Execute Packets in a Fetch Packet Figure 428. Pipeline Operation: Fetch Packets With Different Numbers of Execute Packets 4.4.2 Multicycle NOPs Figure 429. Multicycle NOP in an Execute Packet Figure 430. Branching and Multicycle NOPs . . . 4.4.3 Memory Considerations Figure 431. Pipeline Phases Used During Memory Accesses Table 440. Program Memory Accesses Versus Data Load Accesses Figure 432. Program and Data Memory Stalls Figure 433. 8-Bank Interleaved Memory Example 42. Load From Memory Banks Table 441. Loads in Pipeline from Example 42 Figure 434. 8-Bank Interleaved Memory With Two Memory Spaces Interrupts Chapter 5 5.1 Overview 5.1.1 Types of Interrupts and Signals Used Table 51. Interrupt Priorities Page Page 5.1.2 Interrupt Service Table (IST) Figure 51. Interrupt Service Table Overview 5-7InterruptsSPRU733 Figure 52. Interrupt Service Fetch Packet Overview Interrupts5-8 SPRU733 Example 51. Relocation of Interrupt Service Table 5.1.3 Summary of Interrupt Control Registers Table 52 lists the interrupt control registers on the C67x CPU. Table 52. Interrupt Control Registers 5.2 Globally Enabling and Disabling Interrupts Page 5.3 Individual Interrupt Control 5.3.1 Enabling and Disabling Interrupts Example 54. Code Sequence to Enable an Individual Interrupt (INT9) Example 55. Code Sequence to Disable an Individual Interrupt (INT9) 5.3.2 Status of Interrupts 5.3.3 Setting and Clearing Interrupts Example 56. Code to Set an Individual Interrupt (INT6) and Read the Flag Register Example 57. Code to Clear an Individual Interrupt (INT6) and Read the Flag Register 5.3.4 Returning From Interrupt Servicing Example 58. Code to Return From NMI Example 59. Code to Return from a Maskable Interrupt 5.4 Interrupt Detection and Processing 5.4.1 Setting the Nonreset Interrupt Flag 5.4.2 Conditions for Processing a Nonreset Interrupt Interrupt Detection and Processing 5-17InterruptsSPRU733 Figure 54. Nonreset Interrupt Detection and Processing: Pipeline Operation 5.4.3 Actions Taken During Nonreset Interrupt Processing Interrupt Detection and Processing 5-19InterruptsSPRU733 5.4.4 Setting the RESET Interrupt Flag Figure 55. RESET Interrupt Detection and Processing: Pipeline Operation 5.4.5 Actions Taken During RESET Interrupt Processing 5.5 Performance Considerations 5.5.1 General Performance 5.5.2 Pipeline Interaction 5.6 Programming Considerations 5.6.1 Single Assignment Programming Example 510. Code Without Single Assignment: Multiple Assignment of A1 Example 511. Code Using Single Assignment 5.6.2 Nested Interrupts Example 512. Assembly Interrupt Service Routine That Allows Nested Interrupts Example 513. C Interrupt Service Routine That Allows Nested Interrupts 5.6.3 Manual Interrupt Processing Example 514. Manual Interrupt Processing 5.6.4 Traps Example 515. Code Sequence to Invoke a Trap Example 516. Code Sequence for Trap Return Instruction Compatibility Page Page Page Page Page Mapping Between Instruction and Functional Unit Appendix B Page Page Page Page Page .D Unit Instructions and Opcode Maps C.1 Instructions Executing in the .D Functional Unit Table C1 lists the instructions that execute in the .D functional unit. Table C1.Instructions Executing in the .D Functional Unit C.2 Opcode Map Symbols and Meanings Table C2 lists the symbols and meanings used in the opcode maps. Table C2..D Unit Opcode Map Symbol Definitions Table C3.Address Generator Options for Load/Store C.3 32-Bit Opcode Maps .L Unit Instructions and Opcode Maps D.1 Instructions Executing in the .L Functional Unit Table D1 lists the instructions that execute in the .L functional unit. Table D1.Instructions Executing in the .L Functional Unit D.2 Opcode Map Symbols and Meanings Table D2 lists the symbols and meanings used in the opcode maps. Table D2..L Unit Opcode Map Symbol Definitions D.3 32-Bit Opcode Maps .M Unit Instructions and Opcode Maps E.1 Instructions Executing in the .M Functional Unit Table E1 lists the instructions that execute in the .M functional unit. Table E1. Instructions Executing in the .M Functional Unit E.2 Opcode Map Symbols and Meanings Table E2 lists the symbols and meanings used in the opcode maps. Table E2. .M Unit Opcode Map Symbol Definitions E.3 32-Bit Opcode Maps .S Unit Instructions and Opcode Maps F.1 Instructions Executing in the .S Functional Unit Table F1 lists the instructions that execute in the .S functional unit. Table F1. Instructions Executing in the .S Functional Unit F.2 Opcode Map Symbols and Meanings Table F2 lists the symbols and meanings used in the opcode maps. Table F2. .S Unit Opcode Map Symbol Definitions F.3 32-Bit Opcode Maps Page No Unit Specified Instructions and Opcode Maps Appendix G G.1 Instructions Executing With No Unit Specified Table G1 lists the instructions that execute with no unit specified. Table G1.Instructions Executing With No Unit Specified G.2 Opcode Map Symbols and Meanings Table G2 lists the symbols and meanings used in the opcode maps. G.3 32-Bit Opcode Maps Index A B C Page D E F G H Page L M Page N O P R S T U V X Z