Texas Instruments TMS320C67X/C67X+ DSP manual 16. Mpyspdp Instruction Execution

Pipeline Execution of Instruction Types

4.2.14 MPYSPDP Instruction

The MPYSPDP instruction uses the E1 through E7 phases of the pipeline to complete its operations (see Table 4−16). src1 is read on E1 and E2. The lower 32 bits of src2 are read on E1, and the upper 32 bits of src2 are read on E2. The lower 32 bits of the result are written on E6, and the upper 32 bits of the result are written on E7. The MPYSPDP instruction is executed on the .M unit. The functional unit latency for the MPYSPDP instruction is 3. Figure 4−26 shows the fetch, decode, and execute phases of the pipeline that the MPYSPDP instruction uses.

Table 4−16. MPYSPDP Instruction Execution

Pipeline Stage	E1	E2	E3	E4	E5	E6	E7
Read	src1	src1
	src2_l	src2_h
Written						dst_l	dst_h
Unit in use	.M	.M

Figure 4−26. MPYSPDP Instruction Phases

PG

PS

PW

PR DP

DC

E1

E2

E3

E4

E5

E6

E7

6 delay slots

4-32 Pipeline SPRU733