ARM r1p3 manuals
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456 pages 2.86 Mb
2 Cortex-R4 and Cortex-R4FTechnical Reference Manual Copyright 2009 ARM Limited. All rights reserved. 3 Contents Cortex-R4 and Cortex-R4F Technical Reference Preface Chapter 1 Introduction Chapter 2 Programmers Model 4 Chapter 3 Processor Initialization, Resets, and ClockingChapter 4 System Control Coprocessor Chapter 5 Prefetch Unit Chapter 6 Events and Performance Monitor Chapter 7 Memory Protection Unit Chapter 8 Level One Memory System Chapter 9 Level Two Interface Chapter 10 Power Control Chapter 11 Debug 5 Chapter 12 FPU Programmers ModelChapter 13 Integration Test Registers Chapter 14 Cycle Timings and Interlock Behavior Chapter 15 AC Characteristics Appendix A Processor Signal Descriptions 7 List of Tables Cortex-R4 and Cortex-R4F Technical Reference 13 List of Figures Cortex-R4 and Cortex-R4F Technical Reference 22 Chapter 1 Introduction47 Chapter 2 Programmers Model270 Chapter 11 Debug365 Chapter 14 Cycle Timings and Interlock Behavior378 ())(379 14.9 Branches, and , This section describes the cycle timing behavior for the 380 14.10 Processor state updating instructions381 14.11 Single load and store instructions384 14.12 Load and Store Double instructions385 14.13 Load and Store Multiple instructions388 14.14 RFE and SRS instructions389 14.15 Synchronization instructions390 14.16 Coprocessor instructions391 14.17 SVC, BKPT, Undefined, and Prefetch Aborted instructions392 14.18 Miscellaneous instructions393 14.19 Floating-point register transfer instructions394 14.20 Floating-point load/store instructions396 14.21 Floating-point single-precision data processing instructionsThis section describes the cycle timing behavior for all single-precision VFP , and , instructions. This includes arithmetic instructions such as , data and immediate moving instructions such as 397 14.22 Floating-point double-precision data processing instructionsThis section describes the cycle timing behavior for all double-precision VFP , and , , instructions. This includes arithmetic instructions such as , data and immediate moving instructions such as 398 14.23 Dual issue400 Case F2_st, and , instructions, . , and , Case F3b32-bit transfers to and from the floating-point register file , or a miscellaneous processor control instructiona Any single-precision CDPi, excluding , . 32-bit transfers to and from the floating-point register filel. Case F6 As for Case A. 402 15.1 Processor timing403 15.2 Processor timing parameters414 Appendix A Processor Signal Descriptions439 Appendix C RevisionsThis appendix describes the technical changes between released issues of this book. 442 Glossary
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