Digi NS7520 manuals

332 pages1.68 Mb

5Contents
11Using This Guide
R
- About this guide
- Who should read this guide
- 12Whats in this guide
  - This table shows where you can find specific information in this guide:
  - This table describes the typographic conventions used in this guide:
- Conventions used in this guide
  - monospaced type
- 13Related documentation
- Documentation updates
- Customer support
- 16NS7520 Features
  - Key features and operating modes of the major NS7520 modules
    - About the NS7520
- 19NS7520 module block diagram
  - Figure 1 is an overview of the NS7520, including all the modules.
    - Figure 1: NS7520 overview
      - BBUS
      - NS7520
- 20Operating frequency
- 22Packaging
  - Table 1: NS7520 packaging dimensions
    - Packaging
  - 24Figure 3: NS7520 BGA layout
    - NS7520, 177 PFBGA
    - 10
      - Top View, Balls Facing Down
        V1.0
- 25Pinout detail tables and signal descriptions
  - Each pinout table applies to a specific interface and contains the following information:
  - Notes:
  - 26System bus interface
    - 29Table 3: System bus interface signal description
  - 30Chip select controller
    - The NS7520 supports five unique chip select configurations:
      - Table 4: Chip select controller pinout
      - Table 3: System bus interface signal description
      - 31Table 5: Chip select controller signal description
      - Table 4: Chip select controller pinout
  - 32Ethernet interface MAC
    - Table 6: Ethernet interface MAC pinout
    - In this table, GP designates general-purpose.
      - Table 5: Chip select controller signal description
    - 33Table 6: Ethernet interface MAC pinout
    - 34Table 7: Ethernet interface MAC signal description
  - 35No connect pins
  - General-purpose I/O
    - Table 9: GPIO pinout
    - Table 8: No connect pins
    - 36Table 9: GPIO pinout
  - 38System clock and reset
    - This figure shows the timing and specification for RESET_ rise/fall times:
  - 39System mode (test support)
    - Table 12: System mode and system reset pinout
  - 40JTAG test (ARM debugger)
    - Table 14: ARM debugger signal description
    - Table 13: JTAG test pinout
    - 41Figure 4: TRST_ termination
    - Table 14: ARM debugger signal description
  - 42Power supply
    - Table 15: Power supply pinout
- 44ARM Thumb concept
- CPU performance
- 45Working with ARM exceptions
  - 46Summary of ARM exceptions
  - Exception priorities
  - 47Exception vector table
  - 48Detail of ARM exceptions
  - 51Entering and exiting an exception (software action)
- 53Hardware Interrupts
  - FIRQ and IRQ lines
  - Interrupt controller
  - 54Interrupt sources
- 58BBus masters and slaves
- Cycles and BBus arbitration
- 59Address decoding
- 62Signal description
- JTAG support
- 63ARM debug
- System clock generation (NS7520 clock module)
  - External oscillator vs. internal PLL circuit
  - NS7520 clock module block diagram
- 64Using the external oscillator
  - 65External oscillator mode hardware configuration
- 66Using the PLL circuit
  - PLL mode hardware configuration
    - SYS Module
    - 67Figure 5: PLL mode hardware configuration
- 68Setting the PLL frequency
  - PLL Settings register: Setting the PLL frequency on bootup
    - 69Table 21: PLL Settings register bit definition
  - 71PLL Control register: Setting the PLL frequency with the PLL Control register
- 73Reset circuit sources
- 74NS7520 bootstrap initialization
75GEN Module
- 76Module configuration
  - The GEN module is configured as shown:
    - Table 23: GEN module address configuration
- GEN module hardware initialization
- 77GEN module registers
  - System Control register
  - 82System Status register
    - 83Table 25: System Status register bit definition
  - 84Software Service register
  - Timer Control registers
    - 85Register bit definition
      - 86Table 27: Timer Control registers bit definition
  - 87Timer Status registers
    - Address: FFB0 0014 / FFB0 001C
      - Table 28: Timer Status registers bit definition
  - 88PORTA Configuration register
    - 89Table 29: PORTA register bit definition
    - Table 30: PORTA configuration
  - 91PORTC Configuration register
    - 92Table 31: PORTC register bit definition
    - Table 32: PORTC configuration
- 94Interrupts
  - 95Interrupt controller registers
    - 97Table 33: Interrupt Enable registers bit definition
- 100About the MEM module
- MEM module hardware initialization
  - Pin configuration
- 102MEM module configuration
  - Setting the chip select address range
  - 104Memory Module Configuration register
    - Address: FFC0 0000
    - Table 36: MMCR bit definition
    - The Memory Module Configuration register (MMCR) defines basic MEM module configurations.
    - 105Table 36: MMCR bit definition
  - 107Chip Select Base Address register
    - Address: FFC0 0010/20/30/40/50
    - The Chip Select Base Address register defines the base starting address for the chip select.
    - The V bit is set to 1 on hardware reset for chip select 0 only.
  - 111Chip Select Option Register A
    - Address: FFC0 0014/24/34/44/54
  - 115Chip Select Option Register B
    - Address: FFC0 0018/28/38/48/58
    - Table 39: Chip Select Option Register B bit definition
- 116Static memory (SRAM) controller
  - 117Single cycle read/write
  - 118***
    - Burst cycles
- 119NS7520 DRAM address multiplexing
  - Using the internal multiplexer
    - 121Table 40: Internal DRAM multiplexing Mode 0
    - Table 41: Internal DRAM multiplexing Mode 1
  - 122Using the external multiplexer
- 123DRAM refresh
- FP/EDO DRAM controller
  - 124Single cycle read/write
  - FP/EDO DRAM burst cycles
- 125SDRAM
  - 126NS7520 SDRAM interconnect
    - 127Table 42: x32 SDRAM interconnect
    - 128Table 43: x16 SDRAM interconnect
    - 129Table 43: x16 SDRAM interconnect
    - Table 44: x8 SDRAM interconnect
  - 130SDRAM A10/AP support
  - 131Command definitions
  - 132Memory timing fields SDRAM
  - BSIZE configuration
  - 133SDRAM Mode register
    - SDRAM
    - 120
  - 134SDRAM read cycles
    - Figure 11: SDRAM normal read
  - 136SDRAM write cycles
- 138Peripheral page burst size
- 142DMA module
  - Fly-by operation transfers
  - 143Memory-to-memory operation
- 144DMA buffer descriptor
  - 145Buffer descriptor bit definitions
    - Table 47: Buffer descriptor bit definitions
  - 146Buffer descriptor field definitions
    - Table 48: Buffer descriptor field definitions
- 147DMA channel assignments
- 148DMA channel registers
  - All registers are 32-bit unless otherwise noted.
  - Address map
  - 150Buffer Descriptor Pointer register
  - DMA Control register
  - 156DMA Status/Interrupt Enable register
- 158Ethernet transmitter considerations
- 159Ethernet receiver considerations
- External peripheral DMA support
  - 160Signal description
  - External DMA configuration
  - Memory-to-memory mode
- 161DMA controller reset
- 164Ethernet front-end (EFE)
  - 165Transmit and receive FIFOs
  - EFE transmit processing
  - EFE receive processing
  - 166Receive buffer descriptor selection
- 167External CAM filtering
- 168MAC module
  - MAC module block diagram
- 170DMA channel assignments
- EFE configuration
  - 171Table 52: EFE register map
    - EFE configuration
    - 158
  - 172Ethernet General Control register (EGCR) bit definitions
    - Note:
    - Address: FF80 0000 General information These fields should be set only once, on device open:
    - Bits D15:D00 are media control bits, with D07:D00 used in ENDEC mode only.
      - ERX ETX ERXDMA ETXDMA ERXLNG ETXWM ERXSHT EFULLD ERXBAD
      - ERXREG ETXREG ERFIFOH ETFIFOH ERXBR ETXBC
    - 177Table 54: ENDEC control signal cross-reference
  - 178Ethernet General Status register (EGSR) bit definitions
  - 181Ethernet FIFO Data register
  - 183Ethernet Transmit Status register
  - 188Ethernet Receive Status register
  - 192MAC Configuration Register 1
    - 193Table 60: MAC Configuration Register 1 bit definition
  - 194MAC Configuration Register 2
    - Table 60: MAC Configuration Register 1 bit definition
    - 197Table 62: PAD operation
  - 198Back-to-Back Inter-Packet-Gap register
    - Address: FF80 0408
      - Table 63: Back-to-Back Inter-Packet-Gap register bit definition
  - 199Non-Back-to-Back Inter-Packet-Gap register
    - Address: FF80 040C
      - Table 64: Non-Back-to-Back Inter-Packet-Gap register bit definition
  - 200Collision Window/Collision Retry register
    - Address: FF80 0410
      - Table 65: Collision Window/Collision Retry register bit definition
  - 201Maximum Frame register
    - Address: FF80 0414
      - Table 66: Maximum Frame register bit definition
  - 202PHY Support register
    - Address: FF80 0418
      - Table 67: PHY Support register bit assignment
  - 203Test register
    - Address: FF80 041C
      - Table 68: Test register bit definition
      - Table 67: PHY Support register bit assignment
      - 204Table 68: Test register bit definition
  - 205MII Management Configuration register
    - Address: FF80 0420
      - Table 69: MII Management Configuration register bit definition
      - 206Table 70: CLKS field settings
      - Table 69: MII Management Configuration register bit definition
  - 207MII Management Command register
    - Address: FF80 0424
      - Table 71: MII Management Command register bit definition
  - 208MII Management Address register
    - Address: FF80 0428
      - Table 72: MII Management Address register bit definition
  - 209MII Management Write Data register
    - Address: FF80 042C
      - Table 73: MII Management Write Data register bit definition
  - 210MII Management Read Data register
    - Address: FF80 0430
      - Table 74: MII Management Read Data register bit definition
  - 211MII Management Indicators register
    - Address: FF80 0434
      - Table 75: MII Management Indicators register bit definition
  - 212SMII Status register
    - Address: FF80 0438
      - Table 76: SMII Status register bit definition
  - Station Address registers
    - 213Station Address Register 1 Address: FF80 0440
    - Station Address Register 2 Address: FF80 0444
      - Table 78: Station Address Register 2 bit definition
      - Table 77: Station Address Register 1 bit definition
    - 214Station Address Register 3 Address: FF80 0448
      - Table 79: Station Address Register 3 bit definition
      - Table 78: Station Address Register 2 bit definition
  - 215Station Address Filter register
    - Address: FF80 05C0
      - Table 80: Station Address Filter register bit definition
  - 216Register hash table
    - Table 82: HT2 bit definition
    - 217Address: FF80 05D8
      - Table 84: HT4 bit definition
    - Address: FF80 05DC
      - Table 83: HT3 bit definition
        218204
    - 220206
- 224Supported features
- 225Bit-rate generator
- 226Serial protocols
- UART mode
- 227SPI mode
  - 228FIFO management
- 236General-purpose I/O configurations
- 237Serial port performance
- Configuration
- 239Serial Channel registers
  - Serial Channel 1, 2 Control Register A
    - Address: FFD0 0000 / 40
    - 243Receiver interrupts
      - Table 86: Receiver interrupt enable bits
    - 244Transmitter interrupts
      - Table 86: Receiver interrupt enable bits
      - Table 87: Transmitter interrupt enable bits
  - 245Serial Channel 1, 2 Control Register B
    - Address: FFD0 0004 / 44
  - 249Serial Channel 1, 2 Status Register A
  - 258Serial Channel 1, 2 Bit-Rate registers
  - 268Serial Channel 1, 2 FIFO registers
  - 269Serial Channel 1, 2 Receive Buffer Gap Timer
    - Register diagram and bit assignment
      - Table 92: Serial Channel Receive Buffer Gap Timer bit definition
  - 270Serial Channel 1, 2 Receive Character Gap Timer
  - 272Serial Channel 1,2 Receive Match register
  - Serial Channel 1, 2 Receive Match MASK register
    - 273Table 95: Serial Channel Receive Match MASK register bit definition
- 276DC characteristics
  - Table 96: Recommended operating (thermal) conditions
  - Recommended operating conditions
  - 277Input/Output characteristics
    - Table 97 shows DC characteristics for inputs. Table 98 shows DC characteristics for outputs.
      - Table 98: DC characteristics outputs
  - Pad pullup and pulldown characteristics
    - Table 97: DC characteristics inputs
  - Absolute maximum ratings
- 279AC characteristics
  - AC electrical specifications
    - 280Figure 30: System configuration for specified timing
    - Table 100: System loading details
- 281Oscillator Characteristics
  - Figure 31: Oscillator circuit details
    - 268
  - 282NS7520
- 283Timing Diagrams
  - Timing_Specifications
  - 284Reset_timing
  - 285SRAM timing
    - SRAM timing parameters
  - 295SDRAM timing
    - SDRAM timing parameters
      - 288
    - 302SDRAM load mode
    - SDRAM refresh
  - 303FP DRAM timing
    - FP DRAM timing parameters
      - Timing Diagrams
      - 294
    - 308fp_refresh_cycles Fast page refresh (RCYC = 00)
    - Fast page refresh (RCYC = 01)
      - Electrical Characteristics
    - 309Fast page refresh (RCYC = 10)
    - Fast page refresh (RCYC = 11)
  - 310Ethernet timing
    - Ethernet timing parameters
      - Electrical Characteristics
    - 311Ethernet PHY timing
    - Ethernet cam timing
  - 312JTAG timing
    - jtag arm ice timing parameters
    - jtag arm ice timing diagram
    - 313jtag bscan timing parameters
    - jtag bscan timing diagram
  - 314External DMA timing
  - 317Serial internal/external timing
    - Serial external timing characteristics
    - Serial internal timing characteristics
      - Timing Diagrams
      - 304
    - 318synchronous serial internal clock
    - synchronous serial external clock
  - 319GPIO timing
    - GPIO timing parameters
    - GPIO timing diagram
321Index
- A
- B
- C
- 322D
- 323E
- 324F
- G
- 325H
- I
- J
- L
- 326M
- N
- 327O
- P
- R
- S
- 329T
- U
- V
- W