single cycle read/write 103 SRAM timing 271-280

static memory controller. See SRAM controller.

Station Address Filter register 201 station address logic. See SAL. 155 Station Address registers 198 StatusOrIndex field 169, 174 swap instruction 35

SWI exception 35 SWI instruction 32 SYS module 47-60 ARM debug 49

NS7520 bootstrap initialization 60 PLL use 48

reset circuit sources 59 system clock generation 49 test modes 48

system bus interface pinout 12

signal descriptions 15 system clock and reset

pinout 24

signal descriptions 24 system clock generation 49 System Control register 63 system mode (test support)

pinout 25

System Status register 68

T

test modes 48 Test register 189 Thumb architecture 30 timeout interval equations 71 timer 1 interrupts 40

timer 2 interrupts 40 Timer Control registers 70 Timer Status register 73 timing diagrams 269-305 timing specifications 269 transmit FIFO 151

secondary address 168 transmit FIFO interface 214

U

UART 212-213

and CTS handshaking signal 213 and RTS handshaking signal 213 framing protocols 212 synchronous timing mode 213

undefined exception 32, 34

universal asynchronous/synchronous receiver/transmitter. See UART.

using the external oscillator 50 using the PLL circuit 52

V

vector table, exception 31, 33

W

W bit 130, 131

watchdog reset circuit source 59 watchdog timer interrupts 40

I n d e x - 9

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Digi NS7520 manual Undefined exception 32