E l e c t r i c a l C h a r a c t e r i s t i c s

SDRAM burst write

SDRAM burst write

BCLK

TA* (Note-3)

TEA*/LAST* (Note-3) PortA2/AMUX

Non-muxed address Muxed address

write D[31:0]1 BE[3:0]* (DQM)

CS[4:0]*

CAS3* (RAS)

CAS2* (CAS)

CAS1* (WE)

CAS0* (A10/AP) RW*

T1

active

T2

prechg

write

 

 

30

 

 

37

6

 

 

35

 

35

 

9

 

36

 

 

27

 

 

34

 

34

 

 

34

34

34

34

 

34

34

 

A10

 

12

 

 

T2

T2

write

write

T2

T1

write

inhibit

 

30

31

31

 

37

 

13

 

36

 

27

 

34

 

34

 

34

Notes:

1Port size determines which byte enable signals are active:

8-bit port = BE3*

16-bit port = BE[3:2]

32-bit port = BE[3:0]

2The precharge and/or active commands are not always present. These commands depend on the address of the previous SDRAM access. When the active command is not present, parameter #35 is valid during the write (T2) cycle.

3The TA* and TEA*/LAST signals are for reference only.

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Digi NS7520 manual Sdram burst write