D M A c h a n n e l a s s i g n m e n t s

DMA channel assignments

One DMA channel is dedicated to Ethernet receive and one DMA channel is dedicated to Ethernet transmit. The Ethernet receiver has four DMA subchannels, which support the receive buffer descriptor selection feature (see "DMA buffer descriptor," beginning on page 130).

The Ethernet receiver is assigned DMA channel 1 (1A, 1B, 1C, and 1D). The Ethernet transmitter is assigned DMA channel 2.

EFE configuration

Table 52 shows the Ethernet front-end register map. All registers are 32 bits unless otherwise noted.

Note: Reading or writing the MAC configuration registers (address locations 0xFF80 0400 through 0xFF80 05DC) is unreliable without valid clocks on the TXCLK and RXCLK input pins.

Address

Register

Register description

 

 

 

FF80 0000

EGCR

Ethernet General Control register

 

 

 

FF80 0004

EGSR

Ethernet General Status register

 

 

 

FF80 0008

FIFO

Ethernet FIFO Data register

 

 

 

FF80 000C

FIFOL

Ethernet FIFO Data Register Last

 

 

 

FF80 0010

ETSR

Ethernet Transmit Status register

 

 

 

FF80 0014

ERSR

Ethernet Receive Status register

 

 

 

FF80 0400

MAC1

MAC Configuration Register 1

 

 

 

FF80 0404

MAC2

MAC Configuration Register 2

 

 

 

FF80 0408

IPGT

Back-to-Back Inter-Packet-Gap register

 

 

 

FF80 040C

IPGR

Non-Back-to-Back Inter-Packet-Gap register

 

 

 

FF80 0410

CLRT

Collision Window/Retry register

Table 52: EFE register map

1 5 6

N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6

Page 170
Image 170
Digi NS7520 manual EFE configuration, EFE register map, Address Register Register description