E F E c o n f i g u r a t i o n

SMII Status register

Address: FF80 0438

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

CLASH

JAB-

LINK

DUP-

SPEED

 

 

 

 

 

 

 

 

 

 

BER

LEX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register bit assignment

Bits

Access

Mnemonic

Reset

Description

 

 

 

 

 

D31:05

N/A

Reserved

N/A

N/A

 

 

 

 

 

D04

R

CLASH

N/A

MAC-to-MAC with PHY

 

 

 

 

A 1 indicates that MAC-to-MAC mode is selected,

 

 

 

 

but a PHY is detected.

 

 

 

 

 

D03

R

JABBER

N/A

Jabber condition present

 

 

 

 

A 1 indicates that a Jabber condition is present.

 

 

 

 

 

D02

R

LINK

N/A

Link OK

 

 

 

 

A 1 indicates LINK OK.

 

 

 

 

 

D01

R

DUPLEX

N/A

Full-duplex operation

 

 

 

 

1

Indicates full-duplex operation

 

 

 

 

0

Indicates half-duplex operation

 

 

 

 

 

D00

R

SPEED

N/A

100 Mbps

 

 

 

 

1

Indicates 100 Mbps

 

 

 

 

0

Indicates 10 Mbps

 

 

 

 

 

 

Table 76: SMII Status register bit definition

Station Address registers

The station address is used for address comparison of inbound receive packets. The 48-bit address value is held in three registers, each containing 16 bits.

1 9 8

N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6

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Image 212
Digi NS7520 manual Station Address registers, Smii Status register bit definition