Digi NS7520 - page 37

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Pinout and Packaging

Notes:

1RESET output indicates the reset state of the NS7520. PORTC4 persists beyond

the negation of RESET_ for approximately 512 clock cycles if the PLL is disabled.

When the PLL is enabled, PORTC4 persists beyond the negation of RESET_ to

allow for PLL lock for 100 microseconds times the ratio of the VCO to XTALA.

Note that this GPIO is left in output mode active following a hardware

RESET.

2*PORTC[3:0] pins provide level-sensitive interrupts. The inputs do not need to

be synchronous to any clock. The interrupt remains active until cleared by a

change in the input signal level.

Signal descriptions

See Chapter 6, "GEN Module," for signal and configuration information for PORTA and

PORTC.

PORTC02TXCB/

OUT2B_/

DCDB_

LIRQ0/

DONE2_(I) E14 U I/O 2 Pgm’able Out/

Channel 2

DCD/Channel 2

SPI enable

(SEL_)/Channel

2 TXCLK

Level sensitive

IRQ/DMA

channel 4/6

DONE_in

GPIO

signal Serial

signal Other

signal Pin I/O OD Serial channel

description Other

description

Table 9: GPIO pinout

Contents

Main Page Page Page Contents Page Page Page Page Page Using This Guide R About this guide Who should read this guide Whats in this guide This table shows where you can find specific information in this guide: This table describes the typographic conventions used in this guide: Conventions used in this guide monospaced type Related documentation Documentation updates Customer support Page Page NS7520 Features Key features and operating modes of the major NS7520 modules Page Page About the NS7520 NS7520 module block diagram Figure 1 is an overview of the NS7520, including all the modules. Figure 1: NS7520 overview BBUS NS7520 Operating frequency Page Packaging Table 1: NS7520 packaging dimensions Page Packaging Figure 3: NS7520 BGA layout NS7520, 177 PFBGA 10 Top View, Balls Facing Down V1.0 Pinout detail tables and signal descriptions Each pinout table applies to a specific interface and contains the following information: Notes: System bus interface Page Page Table 3: System bus interface signal description Chip select controller The NS7520 supports five unique chip select configurations: Table 4: Chip select controller pinout Table 3: System bus interface signal description Table 5: Chip select controller signal description Table 4: Chip select controller pinout Ethernet interface MAC Table 6: Ethernet interface MAC pinout In this table, GP designates general-purpose. Table 5: Chip select controller signal description Table 6: Ethernet interface MAC pinout Table 7: Ethernet interface MAC signal description No connect pins General-purpose I/O Table 9: GPIO pinout Table 8: No connect pins Table 9: GPIO pinout Page System clock and reset This figure shows the timing and specification for RESET_ rise/fall times: System mode (test support) Table 12: System mode and system reset pinout JTAG test (ARM debugger) Table 14: ARM debugger signal description Table 13: JTAG test pinout Figure 4: TRST_ termination Table 14: ARM debugger signal description Power supply Table 15: Power supply pinout Page ARM Thumb concept CPU performance Working with ARM exceptions Summary of ARM exceptions Exception priorities Exception vector table Detail of ARM exceptions Page Page Entering and exiting an exception (software action) Page Hardware Interrupts FIRQ and IRQ lines Interrupt controller Interrupt sources Page Page Page BBus masters and slaves Cycles and BBus arbitration Address decoding Page Page Signal description JTAG support ARM debug System clock generation (NS7520 clock module) External oscillator vs. internal PLL circuit NS7520 clock module block diagram Using the external oscillator External oscillator mode hardware configuration Using the PLL circuit PLL mode hardware configuration SYS Module Figure 5: PLL mode hardware configuration Setting the PLL frequency PLL Settings register: Setting the PLL frequency on bootup Table 21: PLL Settings register bit definition Page PLL Control register: Setting the PLL frequency with the PLL Control register Page Reset circuit sources NS7520 bootstrap initialization GEN Module Module configuration The GEN module is configured as shown: Table 23: GEN module address configuration GEN module hardware initialization GEN module registers System Control register Page Page Page Page System Status register Table 25: System Status register bit definition Software Service register Timer Control registers Register bit definition Table 27: Timer Control registers bit definition Timer Status registers Address: FFB0 0014 / FFB0 001C Table 28: Timer Status registers bit definition PORTA Configuration register Table 29: PORTA register bit definition Table 30: PORTA configuration Page PORTC Configuration register Table 31: PORTC register bit definition Table 32: PORTC configuration Page Interrupts Interrupt controller registers Page Table 33: Interrupt Enable registers bit definition Page Page About the MEM module MEM module hardware initialization Pin configuration Page MEM module configuration Setting the chip select address range Page Memory Module Configuration register Address: FFC0 0000 Table 36: MMCR bit definition The Memory Module Configuration register (MMCR) defines basic MEM module configurations. Table 36: MMCR bit definition Page Chip Select Base Address register Address: FFC0 0010/20/30/40/50 The Chip Select Base Address register defines the base starting address for the chip select. The V bit is set to 1 on hardware reset for chip select 0 only. Page Page Page Chip Select Option Register A Address: FFC0 0014/24/34/44/54 Page Page Page Chip Select Option Register B Address: FFC0 0018/28/38/48/58 Table 39: Chip Select Option Register B bit definition Static memory (SRAM) controller Single cycle read/write *** Burst cycles NS7520 DRAM address multiplexing Using the internal multiplexer Page Table 40: Internal DRAM multiplexing Mode 0 Table 41: Internal DRAM multiplexing Mode 1 Using the external multiplexer DRAM refresh FP/EDO DRAM controller Single cycle read/write FP/EDO DRAM burst cycles SDRAM NS7520 SDRAM interconnect Table 42: x32 SDRAM interconnect Table 43: x16 SDRAM interconnect Table 43: x16 SDRAM interconnect Table 44: x8 SDRAM interconnect SDRAM A10/AP support Command definitions Memory timing fields SDRAM BSIZE configuration SDRAM Mode register SDRAM 120 SDRAM read cycles Figure 11: SDRAM normal read Page SDRAM write cycles Page Peripheral page burst size Page Page Page DMA module Fly-by operation transfers Memory-to-memory operation DMA buffer descriptor Buffer descriptor bit definitions Table 47: Buffer descriptor bit definitions Buffer descriptor field definitions Table 48: Buffer descriptor field definitions DMA channel assignments DMA channel registers All registers are 32-bit unless otherwise noted. Address map Page Buffer Descriptor Pointer register DMA Control register Page Page Page Page Page DMA Status/Interrupt Enable register Page Ethernet transmitter considerations Ethernet receiver considerations External peripheral DMA support Signal description External DMA configuration Memory-to-memory mode DMA controller reset Page Page Ethernet front-end (EFE) Transmit and receive FIFOs EFE transmit processing EFE receive processing Receive buffer descriptor selection External CAM filtering MAC module MAC module block diagram Page DMA channel assignments EFE configuration Table 52: EFE register map EFE configuration 158 Ethernet General Control register (EGCR) bit definitions Note: Address: FF80 0000 General information These fields should be set only once, on device open: Bits D15:D00 are media control bits, with D07:D00 used in ENDEC mode only. ERX ETX ERXDMA ETXDMA ERXLNG ETXWM ERXSHT EFULLD ERXBAD Page Page Page Page Table 54: ENDEC control signal cross-reference Ethernet General Status register (EGSR) bit definitions Page Page Ethernet FIFO Data register Page Ethernet Transmit Status register Page Page Page Page Ethernet Receive Status register Page Page Page MAC Configuration Register 1 Table 60: MAC Configuration Register 1 bit definition MAC Configuration Register 2 Table 60: MAC Configuration Register 1 bit definition Page Page Table 62: PAD operation Back-to-Back Inter-Packet-Gap register Address: FF80 0408 Table 63: Back-to-Back Inter-Packet-Gap register bit definition Non-Back-to-Back Inter-Packet-Gap register Address: FF80 040C Table 64: Non-Back-to-Back Inter-Packet-Gap register bit definition Collision Window/Collision Retry register Address: FF80 0410 Table 65: Collision Window/Collision Retry register bit definition Maximum Frame register Address: FF80 0414 Table 66: Maximum Frame register bit definition PHY Support register Address: FF80 0418 Table 67: PHY Support register bit assignment Test register Address: FF80 041C Table 68: Test register bit definition Table 67: PHY Support register bit assignment Table 68: Test register bit definition MII Management Configuration register Address: FF80 0420 Table 69: MII Management Configuration register bit definition Table 70: CLKS field settings Table 69: MII Management Configuration register bit definition MII Management Command register Address: FF80 0424 Table 71: MII Management Command register bit definition MII Management Address register Address: FF80 0428 Table 72: MII Management Address register bit definition MII Management Write Data register Address: FF80 042C Table 73: MII Management Write Data register bit definition MII Management Read Data register Address: FF80 0430 Table 74: MII Management Read Data register bit definition MII Management Indicators register Address: FF80 0434 Table 75: MII Management Indicators register bit definition SMII Status register Address: FF80 0438 Table 76: SMII Status register bit definition Station Address registers Station Address Register 1 Address: FF80 0440 Station Address Register 2 Address: FF80 0444 Table 78: Station Address Register 2 bit definition Table 77: Station Address Register 1 bit definition Station Address Register 3 Address: FF80 0448 Table 79: Station Address Register 3 bit definition Table 78: Station Address Register 2 bit definition Station Address Filter register Address: FF80 05C0 Table 80: Station Address Filter register bit definition Register hash table Table 82: HT2 bit definition Address: FF80 05D8 Table 84: HT4 bit definition Address: FF80 05DC Table 83: HT3 bit definition 204 Page 206 Page Page Page Supported features Bit-rate generator Serial protocols UART mode SPI mode FIFO management Page Page Page Page Page Page Page General-purpose I/O configurations Serial port performance Configuration Page Serial Channel registers Serial Channel 1, 2 Control Register A Address: FFD0 0000 / 40 Page Page Page Receiver interrupts Table 86: Receiver interrupt enable bits Transmitter interrupts Table 86: Receiver interrupt enable bits Table 87: Transmitter interrupt enable bits Serial Channel 1, 2 Control Register B Address: FFD0 0004 / 44 Page Page Page Serial Channel 1, 2 Status Register A Page Page Page Page Page Page Page Page Serial Channel 1, 2 Bit-Rate registers Page Page Page Page Page Page Page Page Page Serial Channel 1, 2 FIFO registers Serial Channel 1, 2 Receive Buffer Gap Timer Register diagram and bit assignment Table 92: Serial Channel Receive Buffer Gap Timer bit definition Serial Channel 1, 2 Receive Character Gap Timer Page Serial Channel 1,2 Receive Match register Serial Channel 1, 2 Receive Match MASK register Table 95: Serial Channel Receive Match MASK register bit definition Page Page DC characteristics Table 96: Recommended operating (thermal) conditions Recommended operating conditions Input/Output characteristics Table 97 shows DC characteristics for inputs. Table 98 shows DC characteristics for outputs. Table 98: DC characteristics outputs Pad pullup and pulldown characteristics Table 97: DC characteristics inputs Page Absolute maximum ratings AC characteristics AC electrical specifications Figure 30: System configuration for specified timing Table 100: System loading details Oscillator Characteristics Figure 31: Oscillator circuit details 268 NS7520 Timing Diagrams Timing_Specifications Reset_timing SRAM timing SRAM timing parameters Page Page Page Page Page Page Page Page Page SDRAM timing SDRAM timing parameters Page Page Page Page Page Page 288 SDRAM load mode SDRAM refresh FP DRAM timing FP DRAM timing parameters Page Page Page Page Timing Diagrams 294 fp_refresh_cycles Fast page refresh (RCYC = 00) Fast page refresh (RCYC = 01) Electrical Characteristics Fast page refresh (RCYC = 10) Fast page refresh (RCYC = 11) Ethernet timing Ethernet timing parameters Electrical Characteristics Ethernet PHY timing Ethernet cam timing JTAG timing jtag arm ice timing parameters jtag arm ice timing diagram jtag bscan timing parameters jtag bscan timing diagram External DMA timing Page Page Serial internal/external timing Serial external timing characteristics Serial internal timing characteristics Timing Diagrams 304 synchronous serial internal clock synchronous serial external clock GPIO timing GPIO timing parameters GPIO timing diagram Page Index A B C D E F G H I J L M N O P R S Page T U V W