P i n o u t a n d P a c k a g i n g

GPIO signal

PORTC02

Serial signal

TXCB/

OUT2B_/ DCDB_

Other signal

LIRQ0/ DONE2_(I)

Pin

E14 U

I/O

I/O

OD

2

Serial channel

Other

description

description

Pgm’able Out/

Level sensitive

Channel 2

IRQ/DMA

DCD/Channel 2

channel 4/6

SPI enable

DONE_in

(SEL_)/Channel

 

2 TXCLK

 

 

 

Table 9: GPIO pinout

Notes:

1RESET output indicates the reset state of the NS7520. PORTC4 persists beyond the negation of RESET_ for approximately 512 clock cycles if the PLL is disabled. When the PLL is enabled, PORTC4 persists beyond the negation of RESET_ to allow for PLL lock for 100 microseconds times the ratio of the VCO to XTALA.

Note that this GPIO is left in output mode active following a hardware

RESET.

2*PORTC[3:0] pins provide level-sensitive interrupts. The inputs do not need to be synchronous to any clock. The interrupt remains active until cleared by a change in the input signal level.

Signal descriptions

See Chapter 6, "GEN Module," for signal and configuration information for PORTA and

PORTC.

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Digi NS7520 manual Gpio signal, Serial signal, Other signal, Serial channel Other Description