M e m o r y C o n t r o l l e r M o d u l e

T1

T2

T2

T2

T2

T2

T2

T2

T2

BCLK

CS_

ADDR[31:4]

ADDR[3:1]

000

001

010

011

100

101

110

111

R/W_

WE_

OE_

BE0_

BE1_

DATA

TA_

Figure 8: SRAM synchronous burst read cycle

NS7520 DRAM address multiplexing

The NS7520 can be configured to use an internal DRAM address multiplexer or an external address multiplexer. A combination of the AMUX and AMUX2 bits in the MMCR and the DMUXS bit in the Chip Select Base Address register determines which multiplexer is used.

Using the internal multiplexer

When configured to use the internal address multiplexer, the DRAM address signals are provided on system bus address pins A13:A0.

A 32-bit DRAM peripheral connects to A13 through A2. A 16-bit DRAM peripheral connects to A13 through A1. An 8-bit DRAM peripheral connects to A13 through A0.

w w w . d i g i . c o m

1 0 5

Page 119
Image 119
Digi manual NS7520 Dram address multiplexing, Using the internal multiplexer, 000 001 010 011 100 101 110 111