Digi NS7520 manual Processor interrupts vs. DMA, Receive Fifo interface

S e r i a l C o n t r o l l e r M o d u l e

Little Endian mode configuration. Transmits first the least significant bytes in the word written to the FIFO. For example, the long word 0x11223344 results in the character 0x44 being transmitted first and 0x11 being transmitted last.

Processor interrupts vs. DMA

The transmit FIFO can be filled using processor interrupts or DMA.

When using processor interrupts, the processor can write one long word (4 bytes) of data to the transmit FIFO when the TRDY bit in Serial Channel Status Register A is active high. If the THALF bit in Serial Channel Status Register A is active high, the processor can write four long words (16 bytes) of data to the transmit FIFO. To facilitate an interrupt when either the TRDY or THALF status bit is active, the processor can set one or both of the corresponding interrupt enables — ETXRDY, ETXHALF — in Serial Channel Control Register A. The appropriate interrupt enable bit — SER 1 TX or SER 2 TX — in the GEN module Interrupt Enable register must also be set.

When using the DMA controller, the processor must interface with the DMA channel registers and the DMA buffer descriptor block attached to DMA channels 8 and 10. To facilitate the use of transmit DMA, the ETXDMA bit in Serial Channel Control Register A must be set active high and the serial transmitter interrupts should be disabled.

Receive FIFO interface

The receive FIFO presents up to four bytes of data at a time to the processor interface. The number of valid bytes found in the next read of the FIFO is defined by the information found in the RXFDB field in Serial Channel Status Register A.

The Endian rules described for the transmit FIFO also apply for the receive FIFO; see "Operating in Endian modes" on page 214.

When reading from the receive FIFO, the processor must perform a long word read operation. Each time a read cycle is performed, the receive FIFO goes to the next long word entry. The processor cannot read individual bytes from the same FIFO long word entry.

Processor interrupts vs. DMA

The receive FIFO can be emptied using processor interrupts or DMA.

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