Digi NS7520 manual Non-Back-to-BackInter-Packet-Gap register

E

EDO DRAM 86 burst cycles 111

EDO DRAM controller 109-111 EFE receive processing 151 EFE transmit processing 151 electrical characteristics 261-305 electrical specifications, AC 265 ENDEC

interface 3

Level 1 mode 161 SEEQ mode 161

ENDEC mode and NS7520 pins 163 entering an exception 37 Ethernet FIFO Data register 167

reading from 168 writing to 167

Ethernet front-end.See EFE. Ethernet General Control register 158

ENDEC mode bits 158 media control bits 158

Ethernet General Status register 164 Ethernet interface MAC

pinout 18

signal descriptions 19 Ethernet MAC 3 Ethernet module 149-207

Back-to-BackInter-Packet-Gap register 184

calculating hash table entries 204

Collision Window/Collision Retry register 186

DMA channel assignments for Ethernet 156

EFE configuration 156 EFE module 150-153 features 150

high-level structure 150

receive buffer descriptor selection 152

receive FIFO 151 receive processing 151 transmit FIFO 151 transmit processing 151

Ethernet General Control register 158 Ethernet General Status register 164 external CAM filtering 153

FIFO Data register 167

MAC Configuration register 1 178 MAC Configuration register 2 180 MAC module 154-155

and MII 154 features 154 hierarchy 154

Maximum Frame register 187

MII Management Address register 194

MII Management Command register 193

MII Management Configuration register 191

MII Management Indicators register 197

MII Management Read Data

register 196

MII Management Write Data

register 195 multicast hash table entries 202

Non-Back-to-BackInter-Packet-Gap register 185

PHY Support register 188 Receive Status register 174 register hash table 202-207 SMII Status register 198

Station Address Filter register 201 Station Address registers 198 Test register 189

Transmit Status register 169

I n d e x - 3