M E M m o d u l e c o n f i g u r a t i o n

Memory Module Configuration register

Address: FFC0 0000

The Memory Module Configuration register (MMCR) defines basic MEM module configurations.

Note: The software reset command issued by the GEN module Software Service register has no effect on any MEM Module Configuration registers.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RFCNT

 

 

 

REFEN

 

RCYC

AMUX

A[27]

A[26]

A[25]

AMUX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits

Access

Mnemonic

Reset

Description

 

 

 

 

 

D31:24

R/W

RFCNT

0

Refresh count value

 

 

 

 

Refresh period =

 

 

 

 

[(2*RFCNT + 2) * 2] / FXTALE

 

 

 

 

Defines the refresh period for the memory

 

 

 

 

controller when FP/EDO DRAM or SDRAM is

 

 

 

 

being used. All DRAMs require a periodic

 

 

 

 

refresh cycle. You determine the specific

 

 

 

 

cycle.

 

 

 

 

Note: There is a small performance and

 

 

 

 

 

power penalty for programming a

 

 

 

 

 

refresh period smaller than

 

 

 

 

 

required.

 

 

 

 

The memory controller generates CAS

 

 

 

 

before RAS refresh cycles for all DRAM

 

 

 

 

types.

 

 

 

 

 

D23

R/W

REFEN

0

Enable DRAM refresh

 

 

 

 

0

Disable DRAM refresh

 

 

 

 

1

Enable DRAM refresh

 

 

 

 

Must be set to 1 when DRAMs are used.

Table 36: MMCR bit definition

9 0

N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6

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Image 104
Digi NS7520 manual Memory Module Configuration register, Mmcr bit definition, Refresh count value, Enable Dram refresh