Digi NS7520 manual Signal description, External DMA configuration, Memory-to-memory mode

E x t e r n a l p e r i p h e r a l D M A s u p p o r t

Signal description

Signal	Description
DREQ_	An input to the NS7520, sourced by the external device. All transfers are
	initiated when the external device asserts DREQ_ low. When the external
	device wants a DMA transfer (either read or write), it asserts the DREQ_
	signal. DREQ_ can stay low until all data transfers are complete, or it can be
	removed as needed to control execution of the DMA.
DACK_	An input to the external device, sourced by the NS7520. When a bus
	transaction occurs, the NS7520 asserts DACK_; DACK_ may or may not
	return high between each data transfer.
	The external device can drive write data to the bus as soon as DACK_ is
	active.
DONE_IN	The external device asserts DONE_IN to retire the current DMA descriptor.
	When the NS7520 receives the DONE_IN signal, it closes the current buffer
	and sets the NCIP bit in the DMA Status register. The number of bytes that
	were received is in the buffer length field in the DMA buffer descriptor.
	DONE_IN can be asserted only when DACK_ is asserted.

DONE_OUT The NS7520 asserts DONE_OUT when the L (Last) bit is set in the DMA buffer descriptor and the buffer is empty (retired).

External DMA configuration

The REQ bit in the DMA Control register must be set to 1 (external source) when configuring for external DMA, and the DMA output signals must be selected at GPIO PORTA. All other settings are the same as for any other DMA transfer.

The DMA channel 3/5 signals — DREQ1_, DACK1_, and DONE1_ — are multifunctional and shared with GPIO PORTA. The DMA channel 4/6 signals — DREQ2_, DACK2_, and DONE2_ — are multifunctional and shared with GPIO PORTC.

Memory-to-memory mode

In memory-to-memory mode, one of the source buffer pointers or destination buffer pointers points to the external device (accomplished by tying the device to a chip select). Each movement of data involves two autonomous operations: reading from the source and writing to the destination.

Figure 20 shows the signals needed for external memory-to-memory transfers.

1 4 6 N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6