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Digi NS7520 manual Serial Channel 1, 2 Status Register a, Address FFD0 0008

Models: NS7520

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S e r i a l C o n t r o l l e r M o d u l e

Figure 27 shows the different transmit and receive coding methods.

Figure 27: Data coding example

Serial Channel 1, 2 Status Register A

Address: FFD0 0008 / 48

The receive status bits (D31:16) are stuffed into the StatusOrIndex field in the DMA buffer descriptor when DMA operations are enabled and a buffer is closed. The upper six bits of this register (D31:26) can be cleared by writing a 1 to the respective bit position (used when interrupt-driven). These six bits are updated automatically when a receive buffer is closed.

The receive interrupt pending bits (D15:00) are cleared by writing a 1 to the respective bit position.

Note: All status bits are active high unless an underscore ( _ ) appears in the signal name; in this case, they are active low.

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Digi NS7520 manual Serial Channel 1, 2 Status Register a, Address FFD0 0008

Contents

NS7520 Hardware Reference Page Part number/version 90000353D Release date March Page Contents A p t e r 4 B B u s M o d u l e A p t e r 7 M e m o r y C o n t r o l l e r M o d u l e A p t e r A p t e r 1 0 S e r i a l C o n t r o l l e r M o d u l e D e Who should read this guide About this guideWhat’s in this guide Conventions used in this guideTo read about See Related documentation Documentation updatesCustomer support For Contact informationPage About the NS7520 Key features and operating modes of the major NS7520 modules NS7520 FeaturesO u t t h e N S 7 5 2 7 5 2 0 F e a t u r e s NS7520 overview NS7520 module block diagramOperating frequency Pinout and Packaging NS7520 packaging dimensions Symbol Min Nom MaxPackaging NS7520 pinout and dimensions NS7520 BGA layout Column Description Pinout detail tables and signal descriptionsSystem bus interface Symbol Pin DescriptionSystem bus interface pinout External busADDR6 ADDR7ADDR5 ADDR4Do not USE Signal descriptions System bus interface signal descriptionMnemonic Signal Description Chip select controller Chip select controller pinoutBusy Mnemonic Signal Chip select controller signal descriptionEthernet interface MAC pinout Ethernet interface MACEthernet interface MAC signal description CRS COLNo connect pins No connect pinsSerial Other Pin Serial channel Signal Description General-purpose I/OPORTA3 Rxda DACK1 RTS PORTC4 RXCB/RIB ResetPORTA2 Dsra Amux DSRSerial signal Gpio signalOther signal Serial channel Other DescriptionSystem clock and reset Clock generation and reset signal descriptionSystem clock pinout System mode and system reset pinout System mode test supportPlltst BistenARM debugger signal description Jtag test ARM debuggerJtag test pinout Trst termination Power supply pinout Power supplySignal Pin Description GNDWorking with the CPU CPU performance ARM Thumb conceptWorking with ARM exceptions ARM modeARM performance ARMException priorities Summary of ARM exceptionsException vector table Exception vector tableVector Description Address Reset exception Detail of ARM exceptionsUndefined exception Abort exception SWI exceptionFirq exception IRQ exceptionEntering and exiting an exception software action Entering an exceptionExiting an exception Exception entry/exit summary Reset UndefException entry/exit by exception type Abort PHardware Interrupts Firq and IRQ linesInterrupt controller Interrupt sources W . d i g i . c o m Page BBus Module Cycles and BBus arbitration BBus masters and slavesBBus masters and slaves Module Master SlaveAddress decoding BBus address decodingAddress range Module Page SYS Module Signal description Signal mnemonic Signal name DescriptionJtag support ARM debug System clock generation NS7520 clock moduleExternal oscillator vs. internal PLL circuit NS7520 clock module block diagram Using the external oscillatorExternal oscillator mode hardware configuration PLL mode hardware configuration Using the PLL circuitPLL mode hardware configuration PLL Settings register Setting the PLL frequency on bootup Setting the PLL frequencyPLL Settings register bit definition Bits Access Mnemonic Reset Description D3109 ReservedMHz A87 A65 A40 ND+1 PLL Settings reg Bits Access Mnemonic Reset DescriptionOutput divider PLL multiplierMHz A87 A65 A40 ND+1 PLL Settings reg PLL Control register bit definition PllcntSysclk frequency MHz ND+1 PLL Settings registerReset circuit sources Address bit Name Description NS7520 bootstrap initializationGEN Module GEN module address configuration Module configurationGEN module hardware initialization Address RegisterSystem Control register GEN module registersAddress FFB0 General informationSoftware watchdog enable Bclk output disableSoftware watchdog reset/interrupt select Software watchdog timeout in secondsBus monitor enable Enable access to internal chip registers in CPUUser mode Description Enable ARM CPU Bits Access Mnemonic ResetDMA module test mode Bus interface TEA/LAST configurationCPU disable DMA module resetTA input synchronizer System Status register Last reset caused by external resetSystem Status register bit definition NS7520 revision IDLast reset caused by PLL update Last reset caused by watchdog timerLast reset caused by software reset Product ID defined by external resistor jumpersTimer Control registers Software Service registerSoftware Service register bit definition Address FFB0 000CTimer enable Timer Control registers bit definitionTimer interrupt enable Timer interrupt modeTimer prescaler Timer clock sourceInitial timer count Timer Status registers bit definition Timer Status registersTimer interrupt pending Current timer countPorta mode configuration Porta Configuration registerPorta register bit definition Porta data directionPorta configuration Porta ConfigurationAdata Porta data registerInputs PORTA1 Gpio Gpio OUT SER1CTS DONE1OUT PORTA0 SER1SPISENABLEOutputs IN/SER1DCDPortc mode Portc Configuration registerPortc register bit definition Portc data directionPortc configuration Portc configurationCdata Portc data registerPORTC1 Gpio Gpio OUT LEVELIRQ1=CDIR1 PORTC0 LEVELIRQ0=CDIR0 PORTC30 InterruptsAddress FFB0 0030 / 0034 Interrupt controller registersInterrupt Enable registers bit definition D01 Page Memory Controller Module MEM module pin configuration by memory type Pin configurationMode A2714 A130 CSx About the MEM moduleMode A2714 A130 SdramRAS CAS Setting the chip select address range MEM module configurationMemory controller register map Address Mnemonic RegisterMemory Space Enable Dram refresh Memory Module Configuration registerMmcr bit definition Refresh count valueEnable A27 output Enable external address multiplexingRcyc Refresh cycle countEnable A26 output A27 and A26 bit settingsEnable A25 output AMUX2Chip Select Base Address register bit definition Chip Select Base Address registerBase Base addressDram configuration mode Peripheral page sizeDram address multiplexer select Dram internal address multiplexer mode External TA configurationBurst memory cycle enable Force Bclk at end of memory cycleWrite-protect the chip select EepromValid bit Chip Select Option Register a bit definition Chip Select Option Register aMask Mask AddressWhen DRSEL=0 When DRSEL=1 and DMODE=2’b00When DRSEL=1 and DMODE=2’b01 at full speed Burst access size in beats When DRSEL=1 and DMODE=10Bsize Port sizeWrite cycle mode Read cycle modeOE Ctrl WE CtrlChip Select Option Register B bit definition Chip Select Option Register BSync Static memory Sram controllerSync Write Sync Read Single cycle read/writeAsync Read Burst cyclesUsing the internal multiplexer NS7520 Dram address multiplexing000 001 010 011 100 101 110 111 7 5 2 0 D R a M a d d r e s s m u l t i p l e x i n g Internal Dram multiplexing Mode NS7520 multiplexed address outputsDram Using the external multiplexer FP/EDO Dram controller Dram refreshFP Dram Write FP Dram Read Normal FP Dram bus cyclesFP Dram burst cycles FP/EDO Dram burst cyclesX32 Sdram configuration NS7520 Sdram interconnectX32 Sdram interconnect BA1 X16 Sdram configurationBA0 BA1 Bclk CLK VCC CKEX16 Sdram interconnect NS7520 signal 16M Sdram signal 64M Sdram signalCAS3 RAS CAS2 CAS1 CAS0 UdqmNS7520 signal 16M Sdram signal X8 Sdram configurationsX8 Sdram interconnect Bclk CLK VCC CKESdram A10/AP support Sdram command definitions Command definitionsMux mode X32 X16 CommandCAS latency Bcyc configuration Bsize configurationMemory timing fields Sdram Burst lengthSdram Mode register settings Sdram Mode registerFull Address Field ValueSdram normal read Sdram read cyclesSdram burst read Sdram normal write Sdram write cyclesSdram burst write Example Peripheral page burst sizeWait Bcyc Page DMA Module Fly-by operation transfers DMA moduleDMA fly-by transfers Memory-to-memory operationDMA buffer descriptor DMA buffer descriptor Fly-by modeBuffer descriptor bit definitions Buffer descriptor bit definitionsBit Description Buffer descriptor field definitions Buffer descriptor field definitionsField Description Channel Base address DMA channel peripheral Fly-by mode DMA channel assignmentsDMA channel assignments DMA channel registers Address mapAddress Description Address Description DMA Control register Buffer Descriptor Pointer registerDMA operation mode DMA channel enableDMA Control register bit definition Channel abort requestBurst transfer enable Memory-to-memory modeBTE Channel request source REQSource address increment SincDinc Destination address incrementData operand size Current DMA channel state shown in binaryCurrent DMA channel buffer descriptor index DMA Status/Interrupt Enable register bit definition DMA Status/Interrupt Enable registerError completion interrupt pending Normal completion interrupt pendingNormal completion interrupt enable Premature complete interrupt enableError completion interrupt enable Buffer not ready interrupt enableEthernet transmitter considerations External peripheral DMA support Ethernet receiver considerationsExternal DMA configuration Signal descriptionMemory-to-memory mode Signal DescriptionHardware needed for external memory-to-memory DMA transfers DMA controller resetPage Ethernet Module Fifo Ethernet front-end EFETransmit and receive FIFOs EFE transmit processingEFE receive processing DMA Receive buffer descriptor selectionExternal CAM filtering MAC module MAC module block diagramOther modules in the diagram include EFE configuration EFE register mapAddress Register Register description Supp MaxfTest McfgAddress FF80 Ethernet General Control register Egcr bit definitionsErxetx Erxdmaetxdma Erxlngetxwm Erxshtefulld Erxbad Erxregetxreg Erfifohetfifoh ErxbretxbcEthernet General Control register bit definition Enable transmit DMA Enable transmit FifoDo not set this bit when operating the Ethernet Receiver in interrupt service modeEnable transmit data Fifo half empty interrupt Enable Transmit Data register ready interruptEnable transmit buffer complete interrupt Enable full-duplex operationInvert the transmit clock input MAC software resetPSOS pNA buffer descriptors Insert transmit source addressEndec control signal cross-reference Endec mode and NS7520 pinsExternal interface mode Mode field Output based on EFE CSR bitEthernet General Status register Egsr bit definitions Ethernet General Status register bit definitionRxfdbrxskip Rxregrtxrege Rxfifohtxfifoh Rxbrtxbc Receive register ready Receive Fifo data availableReceive Fifo half full Receive buffer readyTransmit register empty Receive buffer skipTransmit Fifo half empty Transmit buffer completeEthernet Fifo Data register Endec status signal cross-referenceAddress FF80 0008 / FF80 000C secondary address Writing to the Ethernet Fifo Data registerReading from the Ethernet Fifo Data register Ethernet Fifo Data register bit definition Ethernet Transmit Status registerEthernet Transmit Status register bit definition Fifo data FF80Broadcast packet transmitted Packet transmitted OKMulticast packet transmitted Transmit abort late collisionTransmit abort excessive deferral TxaedTxaec Transmit abort excessive collisionsTransmit aborted underrun TxaurTxaj Transmit abort jumboTxdef Transmit CRC errorTransmit packet deferred TxcrcEthernet Receive Status register TxcolcTransmit collision count Receive buffer size in bytes Ethernet Receive Status register bit definitionReceive carrier event previously seen Receive data violation event previously seenReceive packet has dribble bit error Receive packet has CRC errorReceive broadcast packet Receive multicast packetReceive packet has code violation Receive packet is too longReceive packet is too short MAC Configuration Register RoverReceive overflow MAC Configuration Register 1 bit definition Receive enable RX flow controlPass ALL receive frames MAC Configuration Register 2 bit definition Vlan pad enable Auto detect pad enablePAD/CRC enable CRC enablePAD operation Pad operation tableBack-to-Back Inter-Packet-Gap register Back-to-Back Inter-Packet-Gap register bit definitionBack-to-back inter-packet-gap Address FF80 040C Non-Back-to-Back Inter-Packet-Gap registerNon-Back-to-Back Inter-Packet-Gap register bit definition Non back-to-back inter-packet-gap partCollision Window/Collision Retry register bit definition Collision Window/Collision Retry registerCollision window Retransmission maximumMaximum Frame register Maximum Frame register bit definitionMaximum frame length PHY Support register bit assignment PHY Support registerBit mode Enable Jabber protectionTest register Address FF80 041CTest backpressure Test pauseShortcut pause quanta MII Management Configuration register bit definition MII Management Configuration registerReset MII management Clock selectScani Clks field settingsScan increment single scan for read data Clks field Sysclk ratio MHz exampleMII Management Command register bit definition MII Management Command registerAutomatically scan for read data Single scan for read dataMII Management Address register bit definition MII Management Address registerMII PHY device address MII PHY register addressAddress FF80 042C MII Management Write Data registerMII Management Write Data register bit definition MII write dataMII Management Read Data register MII Management Read Data register bit definitionMII read data MII Management Indicators register bit definition MII Management Indicators registerRead data not valid Automatically scan for read data in progressSmii Status register Station Address registersSmii Status register bit definition Station Address Register 1 bit definition Station Address RegisterStation Address Register 2 bit definition Station address octetOCTET3 Station Address Register 3 bit definitionOCTET4 OCTET5Station Address Filter register Address FF80 05C0Station Address Filter register bit definition Multicast hash table entries and bit definitions Register hash tableAddress FF80 05D0 Address FF80 05D4Address FF80 05DC Address FF80 05D8HT2 bit definition HT3 bit definitionCalculating hash table entries W . d i g i . c o m Page W . d i g i . c o m Page Serial Controller Module RTS, CTS, DTR, DSR, DCD, RI Supported featuresBit-rate generator Serial port block diagramSerial protocols Uart modeSPI mode Transmit Fifo interface Fifo managementOperating in Endian modes Terminology What’s being written ValueReceive Fifo interface Processor interrupts vs. DMAUsing DMA Using processor interruptsSPI master mode SignalsConfiguration SPI master transmitter SPI master receiver SPI slave modeSignals SPI slave receiver SPI slave transmitterSPI slave mode 0 and 1 two-byte transfer General-purpose I/O configurationsConfiguration Operating Mode Serial Port Maximum RateSerial port performance N f i g u r a t i o n Serial Channel 1, 2 Control Register a Serial Channel registersAddress FFD0 0000 Serial Channel Control Register aStick parity Parity enableEven parity select Number of stop bitsRemote loopback Enable the transmitter with active CTSLocal loopback General-purpose output 1/General-purposeData terminal ready active Enable receive DMA requestsRequest-to-send active Receiver interrupt conditionEnable transmit DMA requests Receiver interrupt enable bitsReceiver interrupts Transmitter interrupt conditionTransmitter interrupts Transmitter interrupt enable bitsSerial Channel 1, 2 Control Register B Address FFD0 0004Serial Channel Control Register B bit definition SCC mode Enable receive character GAP timerRcgt BitordrEnable active RTS only while transmitting Transmit encodingReceive data encoding Differential Manchester 111. a 1 is Address FFD0 0008 Serial Channel 1, 2 Status Register aCharacter Match1 Serial Channel Status Register a bit definitionCharacter Match2 Character Match3Character GAP timer Buffer GAP timerBgap CgapDCD Current ring indicator stateCurrent data carrier detect state Current data set ready stateReceive framing error interrupt pending Receive parity error interrupt pendingReceive break interrupt pending Receive overrun interrupt pending RrdyReceive register ready interrupt pending Receive Fifo half-full interrupt pending Receive buffer closed interrupt pendingReceive Fifo full Change in RI interrupt pending Change in DCD interrupt pendingChange in DSR interrupt pending Change in CTS interrupt pendingTransmit register empty interrupt pending Transmit Fifo half-empty interrupt pendingTransmit buffer closed interrupt pending Serial Channel 1, 2 Bit-Rate registers Address FFD0 000C / 4CTempty Timing mode Bit-rate generator enableSerial Channel Bit-Rate register bit definition Receive clock sourceTransmit clock source Drive receive clock externalDrive transmit clock external Clkmux BRG input clockTransmit clock invert Receive clock invert If Dpll is not used but you are using If Dpll is not used and you are not usingWhen Dpll is used in the application, TdcrReceive divide clock rate RdcrTransmit internal clock source TicsRics Receiver internal clock sourceWith the 18.432MHz crystal using Xtale as the clock source Max baudrates with different clock sourcesNreg 16X @ 55.296MHz With the 18.432MHz crystal using Sysclk as the clock sourceSerial Channel 1, 2 Fifo registers X1 mode X8 mode X16 modeAddress FFD0 0010 Bit rate examplesAddress FFD0 0014 Serial Channel 1, 2 Receive Buffer Gap TimerData DataRegister diagram and bit assignment Serial Channel 1, 2 Receive Character Gap TimerSerial Channel Receive Buffer Gap Timer bit definition Address FFD0 0018CT value Serial Channel Receive Character Gap Timer bit definitionSerial Channel 1, 2 Receive Match Mask register Serial Channel 1,2 Receive Match registerAddress FFD0 001C / 5C Address FFD0 0020RMMB1 Serial Channel Receive Match Mask register bit definitionRMMB2 RMMB3Page Electrical Characteristics Recommended operating conditions DC characteristicsRecommended operating thermal conditions Sym Parameter Conditions Min Typ Max UnitPad pullup and pulldown characteristics Input/Output characteristicsDC characteristics inputs DC characteristics outputsInternal pullup characteristics AC electrical specifications AC characteristicsAbsolute maximum ratings Maximum voltage ratingsSystem loading details Estimated Signal Load pF Device loadsPORTA3, PORTA1, PORTC3, PORTC1 MDC, MDIO, TXEN, TXER, TXD30Signal Derating ns/pF Oscillator CharacteristicsOutput buffer derating by load capacitance MDC, TXD30, TXER, TXEN, TDONS7520 TimingSpecifications Timing DiagramsResettiming Reset timing parametersNum Description Min Typ Max Units Sram timing Sram timing parametersNum Description Min Max Unit CS* controlled read wait = Sram readSram burst read CS* controlled read wait = 0, Bcyc = CS controlled write internal and external, wait = Sram writeSram burst write OE* controlled read wait = Sram OE readSram OE burst read WE* controlled write wait = Sram WE writeSram WE burst write Sdram timing parameters Sdram timingSdram read, CAS latency = Sdram readActive Read Inhibit Prechg Bterm Sdram burst read Sdram burst read Sdram write Sdram writeSdram burst write Sdram burst writeSdram refresh Sdram load modeFP Dram timing parameters FP Dram timingFast Page read FP Dram readFast Page burst read FP Dram burst readFast Page write FP Dram writeFast Page burst write FP Dram burst writeFast page refresh Rcyc = FprefreshcyclesCAS3 CAS2 CAS1 CAS0 RF1 RF2 RF3 RF4 RF5 RF8 Ethernet timing parameters Ethernet timingEthernet cam timing Ethernet PHY timingJtag timing Jtag arm ice timing diagramJtag arm ice timing parameters Num Description Min Max UnitsJtag bscan timing parameters Jtag bscan timing diagramExternal DMA timing parameters External DMA timingFly-by external DMA Memory-to-memory external DMA Serial external timing characteristics Serial internal timing characteristicsSerial internal/external timing 2T SYSSynchronous serial external clock Synchronous serial internal clockGpio timing diagram Gpio timingGpio timing parameters Page Index CPU Non-Back-to-BackInter-Packet-Gap register FP Dram Portc NET+ARM PORTC0 Receiver interrupts 229 transmitter interrupts Undefined exception 32 Page