Digi NS7520 manual Wait Bcyc

M e m o r y C o n t r o l l e r M o d u l e

The bus master begins a 16-byte burst cycle starting at ’hC. It expects to receive four long words of data from address offsets ’hC, ’h10, ’h14, and ’h18. The memory controller will allow the full burst because BSIZE allows a total of 16 long words to be accessed.

The memory controller does a normal access to address ’hC using the WAIT field to determine access timing. The memory controller then follows with 3 burst beats to address offsets ’h10, ’h14, and ’h18 using the BCYC field to determine the access timing.

The memory peripheral properly delivers the data at address offset ’hC. The peripheral, however, has trouble providing the value at ’h10. The NS7520 is operating with the BCYC burst timing and the memory peripheral needs an access cycle using the WAIT timing, as the access address has crossed the memory peripheral’s page boundary.

If a memory peripheral has a page size less than 64 bytes, then, the memory peripheral can interface only with the NS7520, using burst cycles, when both the WAIT and BCYC fields result in the same number of clock cycles for normal and burst cycles.

You can use one of these combination:

WAIT BCYC

01

12

23

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