E l e c t r i c a l C h a r a c t e r i s t i c s

SDRAM burst read

SDRAM read, CAS latency = 1

BCLK

TA* (Note-5)

TEA*/LAST* (Note-5) PortA2/AMUX Non-muxed address Muxed address BE[3:0]* (DQM)

read D[31:0] CS[4:0]* CAS3* (RAS) CAS2* (CAS) CAS1* (WE) CAS0* (A10/AP) RW*

T1

active

read

T2

prechg

nop

 

 

 

30

 

 

37

37

6

 

 

 

35

 

35

 

36

 

 

 

 

 

 

10

27

 

 

 

34

 

34

 

 

 

34

34

34

34

 

 

 

34

34

34

 

A10

 

 

12

 

 

 

T2

T2

nop

nop

11

 

T2

T1

bterm

inhibit

 

30

31

31

 

36

 

27

34

34

Notes:

1Port size determines which byte enable signals are active:

8-bit port = BE3*

16-bit port = BE[3:2]

32-bit port = BE[3:0]

2The precharge and/or active commands are not always present. These commands depend on the address of the previous SDRAM access.

3If CAS latency = 3, 5 NOPs occur between the read and burst terminate commands.

4If CAS latency = 3, 3 inhibits occur after burst terminate.

5The TA* and TEA*/LAST signals are for reference only.

w w w . d i g i . c o m

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Digi NS7520 manual Sdram burst read