D M A b u f f e r d e s c r i p t o r

DMA buffer descriptor

All DMA channels operate using a buffer descriptor. Each DMA channel remains idle until enabled using the CE bit in the DMA Control register (see "DMA Control register," beginning on page 136). When started, a DMA channel reads the DMA buffer descriptor pointed to by the Buffer Descriptor Pointer register (see "Buffer Descriptor Pointer register," beginning on page 136). When the current descriptor is completed, the next descriptor is accessed from a circular buffer.

Each DMA buffer descriptor requires two 32-bit words for fly-by mode and three 32- bit words stored on four-word boundaries for memory-to-memory operations. Multiple buffer descriptors are located in 1024-byte circular buffers. The first buffer descriptor address is provided by the DMA channel’s buffer descriptor pointer. Subsequent buffer descriptors follow the first descriptor. The final buffer descriptor is defined with its W (wrap) bit set. When the DMA channel encounters the W bit, the channel wraps around to the first descriptor. If the DMA channel does not encounter a descriptor with the W bit set, the channel wraps at the 1024-byte address boundary.

Each DMA channel can address a maximum of 128 fly-by or 64 memory-to-memory buffer descriptors. Figure 18 and Figure 19 show each descriptor type.

 

31

30

29

28

16

15

0

Offset + 0

W

I

L

 

 

 

Buffer pointer

Offset + 4

 

 

 

Status

 

F

Buffer length

Figure 18: DMA buffer descriptor — Fly-by mode

 

31

30

29

28

16

15

 

0

Offset + 0

W

I

L

 

Source buffer pointer

 

Offset + 4

 

 

 

Status

 

F

 

Buffer length

Offset + 8

 

 

 

 

Destination buffer pointer

 

Offset + C

 

 

 

 

Reserved

 

Figure 19: DMA buffer descriptor — Memory-to-memory mode

1 3 0

N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v . D 0 3 / 2 0 0 6

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Image 144
Digi NS7520 manual DMA buffer descriptor Fly-by mode